Intel Corp (INTC)

[wbmw]

Elmer, as Spokeshave indicated, I don't see where the binning would come into play. Processors are designed so that the PLL logic can work at a large variance of multipliers, but would it make sense for chipsets to do the same? We know that the highest performance comes from running various busses at the same frequency, so that the data is synchronized and clock gating mechanisms need not be used. Not only does this simplify the design in some cases, but it also increases performance (clock gating often adds periodic empty cycles so that data can synchronize). While we know that FSB clocking is flexible in the extreme (look at CPU overclocking as an example), many other busses are spec'ed to run at very specific speeds, and too much variation can cause instabilities. PCI and PCI Express will be examples of this. In order to bin out their chipsets, Intel would need to support a ton of various permutations in the clock gating scheme, as well as large variations in operating frequencies for the FSB and memory interfaces. I believe this adds too much to validation to be worth it. In terms of simply overclocking the chipset itself, remember all the interfaces, and the clock gating that will required in between each of them.