United States Patent 8,015,471
Hepler September 6, 2011
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Symbol rate hardware accelerator
Abstract
A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The address generator(s) generate(s) an address for accessing the first buffer, the second buffer and a shared memory architecture (SMA). The translation ROM is used in generating a translated address for accessing the first buffer and the second buffer. The controller sets parameters for the CRC generator, the convolutional encoder and the address generator, and performs a predefined sequence of control commands for channel processing, such as reordering, block coding, parity tailing, puncturing, convolutional encoding, and interleaving, on the information bits by manipulating the information bits while moving the information bits among the first buffer, the second buffer, the SMA, the CRC generator, and the convolutional encoder.
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Inventors: Hepler; Edward L. (Malvern, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 11/776,610
Filed: July 12, 2007
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Related U.S. Patent Documents
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Application Number Filing Date Patent Number Issue Date
60830909 Jul., 2006
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Current U.S. Class: 714/766 ; 712/221
Current International Class: G11C 29/00 (20060101)
Field of Search: 714/766 712/221
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