Advanced Micro Devices Inc (AMD)

[oc detective]

But even presenting individual FSBs to each Xeon would hardly add anything... The NB's bandwidth to memory itself would have to double as well to keep pace with the Opteron. But that extra memory bandwidth would be useless in a 1P system. Xeon really needs a custom NB for each value of N in N-way systems.

It's the integration of 1 NB's worth of resources into each Opteron that lets it scale so efficiently.

Which is probably why Intel are now talking about having integrated memory controllers in the future (presumably in the server sector initially)