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Wednesday, May 11, 2005 1:38:08 AM
Clearly, the fact that every Opteron you add to a system adds not just computational logic but another share of memory capacity, memory bandwidth, and system interconnect bandwidth (at the cost of slightly higher average memory latency) is a significant factor. It's not just that there are multiple pathways, its that the resources themselves scale.
Unfortunately, all the Xeons on the same bus have to share the same path to main memory...
But even presenting individual FSBs to each Xeon would hardly add anything... The NB's bandwidth to memory itself would have to double as well to keep pace with the Opteron. But that extra memory bandwidth would be useless in a 1P system. Xeon really needs a custom NB for each value of N in N-way systems.
It's the integration of 1 NB's worth of resources into each Opteron that lets it scale so efficiently.
fpg
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