United States Patent 7,822,106
Hackett October 26, 2010
--------------------------------------------------------------------------------
Enhanced rake structure
Abstract
A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.
--------------------------------------------------------------------------------
Inventors: Hackett; William C. (Doylestown, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 10/793,025
Filed: March 4, 2004
--------------------------------------------------------------------------------
Related U.S. Patent Documents
--------------------------------------------------------------------------------
Application Number Filing Date Patent Number Issue Date
10034874 Dec., 2001 6771693
--------------------------------------------------------------------------------
Current U.S. Class: 375/148 ; 375/130
Current International Class: H04B 1/69 (20060101)
Field of Search: 375/148,143,142,150,130,133,134,136,137,147,335,342,441
