Intel Corp (INTC)

[mike306oh]

Chip, do you believe:

1. 2 to 3 atomic layers gate oxide

2. below 50 angstroms diffused layers

3. below 50 nm feature size

are practical?

If the answer is no for any of the above, you got youself the answer. Further downsizing CMOS will not be possible for too long. What's your good alternative?

W/o being trying to follow in your footsteps (being rude), if it were for people like you, we'll still use horses to move around, while some of us are dreaming at flying cars.

Mike
---------------------
Exactly. Having gone from designing in 6 um NMOS
to 90 nm CMOS over the first quarter century of my
adult life I have very little tolerance for tech prophets
claiming the "end is near" for mainstream semi tech-
nology. I have heard it a hundred times before starting
around 1.5 um.