Rambus (RMBS)

[calbiker]

Seems to me the DRAM performance will be dictated by the serial bus.

That's probably correct. And seems to be a weak point of the design. Their design rule is to have the bus 6 times faster than the DRAM. This sounds like a potential bottleneck already. The max bus speed (right now) is designed for DDR 800. Six times 800 Mhz means the serial bus max speed is 4.8 Gbps. With 14 parallel lines, the peak data rate is:

4.8 Gbps/line * 14 lines * 8b/10b / 8b/B = 6.72 GB/s

A 64-bit DDR 800 DIMM has a peak bandwidth of 6.4 GB/s, just filling up the entire bus bandwidth. On top of that, this serial bus must also carry address and control data, not to mention streaming data from other FB-DIMMs on this bus. Sounds like a major bottleneck.

So, would XDR increase performance? Perhaps. Intel does state there's an upgrade path to DDR3. DDR3 would see the same bandwidth limitations that XDR would encounter. So there must be a fix. Perhaps increase the serial bus speed to 10 Gbps? That's awful fast. It's iffy if they can accomplish that. Don't know why they didn't increase the number of lanes from the get-go.