Intel Corp (INTC)

[SemiconEng]

The best "knob" to turn is poly linewidth ... Thus it is both a litho and etch issue. Both of these need to be closely monitored. I have seen the poly etch bias be as hard to control as the litho bias. I have also seen etch bias from isolated to dense features and PFET versus NFET biases at etch.
At least in Litho, some of these can be corrected on the reticle. Pushing the process just reduces the margin for devices to be out of spec (Ioff, BVdss, Vt, ...).
Make It So,
Yousef

Yeah, what he said, but it's also critical for other layers. For example, if your Contact Layer pads are too small, Post Etch, the VIA interconect might miss the Pad alltogether, resulting in only a partial connection between layers, and resulting in dead die. But Yousef is right about speed. Poly is frequently referred to by P.E.'s as "The Speed Layer", for reasons Yousef described. Litho creates the patterns, but depending on the Etch Bias, the Post Etch Critical Dimensions are the "Data Feedback", to the Litho folks to tell them if their Focus/Exposures are set correctly.

Thanks Yousef!!!

Semi