Programmable chips reach high-end communication applications
Maury Wright, Editor-in-Chief -- CommVerge, 7/3/2002
Vendors of FPGAs (field programmable gate arrays) continue to amaze with denser chips and—more importantly—more potential speed and processing power. FPGAs were once limited to prototype and low-volume applications, but are now finding a place in high-end products like network gear. In fact, full-fledged ASIC (application-specific integrated circuit) development is hard to justify unless companies know they will be making millions of units. So communication systems will increasingly be based on off-the-shelf network or packet processors augmented by FPGAs.
Actel has targeted exactly this trend in system design with its new Axcelerator (AX) family of FPGAs. Actel claims that FPGAs based on static RAM (SRAM), which are the highest volume sellers today, have architectural limitations when it comes to handling high-speed data streams. The AX architecture uses antifuse technology, which has been primarily limited to specialty applications in the past but which addresses the speed issue.
With internal 500-MHz performance, the AX series is designed to handle data streams used in a number of 10-Gbit/sec standards including SONET, Fibre Channel, and 10-Gbit Ethernet. The architecture can process a 64-bit data path at 156 MHz, thereby achieving the 10-Gbit/sec speeds.
SRAM-based FPGAS can typically handle only half that rate, meaning system designers must use more datapaths and add a significant amount of circuit overhead, including pipelines and serializer/deserializer circuits. Actel will offer the AX family in devices with gate counts ranging from 125,000 to 2 million.
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