Actel opts for asic-like structure for its FPGA
By Chris Edwards
EE Times
1 July 2002 (11:23 a.m. GMT)
The tendency for FPGAs to resemble asics in the
way they are designed has taken another step
with the development by Actel of its AX
architecture.
The AX is an FPGA based on metal-metal
anti-fuses so that the interconnect fuses sit
above the logic modules. The company claims
this is intrinsically faster than an SRAM-based
design, where the signal has to pass through
multiple vias to get to each programming
element.
But Actel has tried to eke more speed out of the
design by adding buffers to the architecture.
Similar to their use in hardwired asics, the
buffers reduce the load of high-fanout circuits on
driving transistors and help to cut the impact of
that load on switching time.
Bill Bailey, marketing manager for Axcelerator,
the first product to be derived from the AX, says
using buffers is more efficient space-wise than
replicated logic. Buffer insertion can be chosen
by the synthesis tool.
"We have been working with synthesis vendors to take better advantage of
the technique," he said.
Each buffer sits in a cluster of logic cells. The SuperCluster, as Actel terms it,
is a collection of combinatorial and registered logic cells design so that
independent paths can use adjacent cells.
"There is a very loose association of logic modules in a cluster," said Bailey.
But by tying cells together, the place-and-route tool can take advantage of
fast paths lying between the combinatorial and registered cells.
Based on a 0.15µm, seven-layer metal process, the Axcelerator can support
"80 to 90% of the performance requirements of the asic market," said
Bailey. It will run at 156MHz assuming six levels of logic between registers
and with a fanout of two between logic gates.
AX aimed at Comms
Actel has aimed the first example of the AX architecture squarely at the
comms industry and tuned the design of the Axcelerator to suit.
The company has put hardwired fifo logic around each memory block to
buffer data expected to come from 10Gbit/s Ethernet and OC-192
front-ends.
Because comms designs generally contain a multitude of interrelated clocks,
the company has redesigned the on-chip clocking system to handle eight
global clock trees that can be sourced from logic elements on-chips or
elsewhere.
Bailey said: "You can build extra clocks out of regular routing and the
segmentable clocks can be used for global signals other than clocks."
The AX architecture will ultimately form the basis of another Actel
comms-FPGA family, the BridgeFPGA. This will incorporate hardwired cores
that implement commonly used high-speed serial comms interfaces,
wrapped around a core of programmable logic.
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