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Wednesday, June 30, 2004 6:16:20 AM
(from x86-secret.com)
Englishish:
Index of reliability: 5/8 (Credible)
We recently could discuss with a Russian engineer AMD being occupied particularly of the implementation Dual Core of the futures CPUs AMD64. Here of which some interesting information that we have to share. To return to the architecture of these processors, they is relatively simple, it acts in fact of two dies of Opteron as we currently know them, with two L2 masks of 1 Mo each one. These two cores are connected sets via an external bus that AMD calls SRI (System Request Interfaces). These two cores, on the other hand, share the external resources of connections for their making it possible to function on same Socket 940 as CPUs with only one core. In light, that means that both cores will have only one controller report as well as three links Hyper-Transport.
Let us speak now about the date of output: First CPUs Bi-Core, of Will choose, will be available in mass towards the end of the year 2005. Those are compatible on the level of the package with Opterons Socket 940 current, but not forcing on the level of the mother board. Indeed, the futures Opterons Dual Channels will function with requirements in electric term of consumption on the level of the Opteron futures 90 Nm and not on the level of current Opteron 130 Nm. The TDP as of the these processors will be of 95 Watts and the introduction frequency will be 1.6 Ghz, this frequency should quickly go up to 2 Ghz. Another direct information without relationship with Dual Core, AMD envisages a transition towards a new type of Socket in first half of the year of the year 2006. The first processor to use it will be Opteron x66 (166, 266, 866). We could not obtain our source of precision on this model. But we let us have itself that it will act is of Opteron 90 Nm Bi-Core to 2 GHz, evening of Opteron 65 Nm...
Englishish link:
http://www.worldlingo.com/wl/translate?wl_lp=FR-en&wl_glossary=gl6&wl_fl=2&wl_ucp=1&...
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