Intel Corp (INTC)

[SemiconEng]

It does seem to confirm what SemiconEng has been saying - there is nothing wrong with Intel's 90nm process.


I know it seems counter intuitive for me to keep saying that, with all of Prescott's issues, and all I have is ancedotal evidence, and Process experience, but here's why I think so......

First, all that saying there's nothing wrong with the process means, is that the films are being layed down with the proper thicknesses, with expected uniformities, the Litho Patterns are hitting their critical dimensions, The Etchers are creating the correct profiles, and the cleaning processes are holding down the defect densities. In order for intel to transfer from the Development Site to the High Volume Site, the Process must achive a certain Yield, or it won't be transferred. All these things MUST have happened for the 90nm process, or intel wouldn't have transferred it to the first HVM Site in New Mexico, and they certainly wouldn't be "ramping it". No, you only ramp the wafer starts if the process is working.

Secondly, If Prescott didn't hit it's intended performance goals, then IMO something Must be wrong with the design. You fix the design with resteppings. If there was no issue with Prescott's design, then IMO, it wouldn't already be on it's 4th major restepping, and the "D" in the D0 stepping verifies that. I wouldn't even be surprised if there might already be an "E" stepping on the drawing board. Maybe it's the longer pipeline, maybe something else, I don't know what, that's more Chipguy's turf then mine. One thing's for sure, I agree with him that going with a straight Northwood shrink would have been the better way to go. I guess fans of that path, didn't get to make the decision.

Semi