By all accounts, Tukwila will be a brand new IPF micro-architecture with the innovations of the ADTers built inside. I don't see much that can be added to x86 that can stand up to that.
There is very little information in that statement to back up the bold conclusion that terminates it. What exactly are the ADT'ers big improvements?
I think so. Take a Madison and Gallatin CPU with 1M of L3 cache, and the Gallatin seems to outperform. However, I think comparing both CPUs with 6M of cache would show Madison to be the victor. We are already seeing diminishing returns for x86 CPUs with large caches. Outside of SPEC, the Pentium 4 Extreme Edition has few applications where it can boast more than a few percent gain over the equivalently clocked Northwood. The scalability characteristics are simply different between x86 and IPF, but most people assume they are the same. That's a logical fallacy.
You seem to be forgetting the Hammer, which is beating the EE with 1/3 the cache and 2/3 the clockspeed. I think the scalability issues are unique to the NetBurst architecture, not the x86 and AMD64 ISAs themselves.
Doubtful. The Gallatin core has 2M of cache and the size is close to 240mm^2. A dual core implementation with 4M of shared cache would be 480mm^2, and you wouldn't want to put less than double the amount of cache on a dual core CPU. Madison is ~370mm^2. At 90nm, when dual core becomes more feasible, Intel is already designing a dual core IPF chip with 24M of cache - Montecito. It will probably be more than 500mm^2 unless they somehow found a way to compact the core or the cache quite a bit smaller than it is now. I'm sure you could do many things to an x86 core with that kind of budget, but the argument is kind of moot, since the best way to take up die area right now is to add more cache, and 24M of cache is not going to help an x86 processor to perform better.
Nice strawman argument, packaged up nice and neat in half a sentence: "...the best way to take up die area right now is to add more cache, and 24M of cache is not going to help an x86 processor to perform better." I hold a different opinion: 500sqmm would be able to contain 4 90nm 1ML2 Opteron cores, with enough left over for several more MB of shared L3. Such a chip could run it's internal HTT interfaces at core speed, expose 4 more to the outside world, have 8 (eight!) 64-bit memory channels, and consume maybe 150-200w. This is not stretch technology, it's a very conservative model (assuming the basic 500sqmm premise). And yet I bet it would trounce your 24MB Montecito. Don't forget, the 6MB Itaniums of today are hardly crushing the 1MB Opterons of today. There's no reason to think that slapping even more cache onto an Itanium will suddenly start yeilding big benefits.
As long as it is going into a market with four-figure ASPs, the die size is irrelevant. By the 2007/8 time frame, 45nm features will allow far more to be done to the design, and I think the added size required for IPF implementations will be small relative to the allowable budget, and that would allow for more mainstream uses.
IMHO trying to predict what will happen in the processor market 4 years down the road is like trying to predict the Oscars 4 years down the road. Pointless. Think about the changes that have occured in the last year alone. Who knows what paradigms may emerge? Asymmetric multicore functionality? Integrated media/GPU/network/vector/encryption processors? Slap a dedicated vector co-processor onto the SRQ of a 90 or 65nm Hammer and expose HW API's... How about reconfigurable logic on die? I can think of a million ways to use 24MB's worth of transistors other than cache. This whole "x86 can't scale like Itanium" argument is pure short-sighted bunk, a red herring.
fpg
AI
