fpg, Re: By all accounts, Tukwila will be a brand new IPF micro-architecture with the innovations of the ADTers built inside. I don't see much that can be added to x86 that can stand up to that.
>> There is very little information in that statement to back up the bold conclusion that terminates it. What exactly are the ADT'ers big improvements?
Historically, people have come to expect great things from the former Alpha Design Team. I and others have high expectations set on them. You are of course free to assume otherwise.
Re: You seem to be forgetting the Hammer, which is beating the EE with 1/3 the cache and 2/3 the clockspeed. I think the scalability issues are unique to the NetBurst architecture, not the x86 and AMD64 ISAs themselves.
It has nothing to do with the cache. 512KB Athlon 64 isn't much slower than 1MB versions. Opteron's already past the sweet spot, in a sense. You could tag on an extra 5MB to be cache equal with Madison, and I don't think it would make much of a difference.
Re: I hold a different opinion: 500sqmm would be able to contain 4 90nm 1ML2 Opteron cores, with enough left over for several more MB of shared L3. Such a chip could run it's internal HTT interfaces at core speed, expose 4 more to the outside world, have 8 (eight!) 64-bit memory channels, and consume maybe 150-200w. This is not stretch technology, it's a very conservative model (assuming the basic 500sqmm premise). And yet I bet it would trounce your 24MB Montecito.
Besides underestimating Montecito, you are forgetting one thing: Montecito is a reality, while the processor you describe is a figment. AMD can't design a 500mm^2 die because they don't have 300mm wafers, and that size die is liable to zero yield on anything less. It will be interesting to see how AMD's dual core Opteron competes with the dual core, multithreaded, 800MT/s, 24M Montecito. I expect Montie to outperform on most enterprise benchmarks by at least 50% over Opteron, maybe more.
Re: IMHO trying to predict what will happen in the processor market 4 years down the road is like trying to predict the Oscars 4 years down the road. Pointless. Think about the changes that have occured in the last year alone. Who knows what paradigms may emerge? Asymmetric multicore functionality? Integrated media/GPU/network/vector/encryption processors? Slap a dedicated vector co-processor onto the SRQ of a 90 or 65nm Hammer and expose HW API's... How about reconfigurable logic on die? I can think of a million ways to use 24MB's worth of transistors other than cache. This whole "x86 can't scale like Itanium" argument is pure short-sighted bunk, a red herring.
You bring up some good points, but all those things you mention requires serious design and validation efforts, while cache nearly comes for free. How much more complex of a design is a 6M Montecito over a 24M Montecito. Adding the cache must have been a no brainer. Just come up with the largest die size you can reliably make and then fit the available space with SRAM. Essentially free performance, especially in the large multiprocessor systems, such as Superdome and Altix 3000.
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