Lightwave Logic Inc (LWLG)

[tkg]

I've seen increased online chatter recently re Tesla's Dojo chip...emphasis on low voltage electronics...;)

January 19th, 2023

Samsung, Intel, TSMC, and many other device makers are focusing on optimizing die-to-die and die-to-package interconnects in various architectures, whether constructed vertically with microbumps, hybrid bonding, and bridges, or horizontally with fan-out redistribution layers. Deciding how and where interconnections will be formed is a becoming a big part of system integration.
The number of packaging options is growing because many of these new designs are highly customized for specific applications. So how they are constructed and connected often depends on the amount and type of data that needs to be processed, where it needs to be processed, and how much power is available. Case in point: Tesla’s D1 Dojo chip, a 50-billion transistor chip used to train AI models inside Tesla’s data center. The emphasis here is on massive data throughput, using highly parallel computation with built-in flexibility, said Pete Bannon, vice president of low voltage electronics at Tesla, in a recent presentation.
Tesla’s device includes 25 D1 chiplets in an array, based on TSMC’s Integrated Fan-Out (InFO) technology. Bannon said the device can achieve 9 petaflops, moving at a speed of 36 terabytes per second using 576 lanes of an I/O ring. It also includes 3 narrow RDL layers and 3 thick RDL layers.
TSMC’s roadmap, meanwhile, calls for new low-resistance interconnects that can decrease resistance by 40%. Fabricated not by damascene but by subtractive metal reactive ion etch with airgap instead of dielectric, the scheme can decrease capacitance by 20% to 30%, and eventually 2D interconnect materials to replace copper interconnects, according to Yuh Jier Mii, TSMC’s senior vice president of R&D. “With less resistivity, there is a potential for future scaling with enhanced interconnect performance,” Mii said in a recent presentation