LWLG- The Tip of the SiPh Spear
CMOS foundries respond slowly to PIC platforms
Some say definitively that hybrid silicon photonics is far from a true CMOS play. Firstly, they point out, PDK libraries are incomplete and not optimized and foundries still expect users to characterize the building blocks.
Others give a more muted response. SiPh foundries are “pretty fixed in their PDKs and recipes because they run in CMOS,” says Michael Lebby. “When you’re a photonics company and have photonics dimensions, components, and designs, it doesn’t automatically fit. It’s actually difficult for the photonics industry to change their recipes/designs to fit the foundry PDKs? Sometimes it’s yes, sometimes it’s no.”
A big concern is whether silicon CMOS foundries are flexible enough for novel modulator/PIC platforms. “It’s an interesting question,” says Lebby. “We’ve seen foundries doing some good work. But this is the start and may require an effort to engineer through, or are we going to have problems?” Silicon foundries are attempting to take all of the new materials—like thin-film lithium niobate, barium titanate, plasmonics, indium phosphide, and others—and integrate them into CMOS platforms. “It’s not easy,” Lebby says.
Another point is that as an industry, silicon photonics still hasn’t clearly defined “hybrid.” For Lebby, it means it isn’t a pure play—it involves a different material. “It can be either frontend or backend,” he explains. “And the reason I say backend is if you look at the electronics industry, we’ve really gone to chip-scale packaging and the photonics industry is definitely heading in that direction. Chip-scale PICs, getting rid of the gold box packaging and the traditional package, chip-on-board and these types of directions are becoming increasingly important.” The packaging ecosystem doesn’t really exist in silicon photonics.
A further sticking point is that modeling software is “at best fair in silicon photonics,” Peter Winzer adds. Tape-outs are low in silicon photonics and it can take nine to 12 months to get chips back. MPWs (multi-project wafers) take even longer and it’s frustrating because it gets into a cycle of iteration, which is needed because there is no ‘first time is right’ design in silicon photonics.”
The IP vendor ecosystem that exists in digital CMOS and to some extent in analog CMOS doesn’t really exist in silicon photonics.
And finally, Winzer continues, “some of the foundries you tape-out with in silicon photonics, if you ask them: ‘Can I scale this up to several thousand wafers per year?’ They say: ‘not with me,’ and you’re stuck because you can’t transfer what you just developed with them to another foundry. You start from the very beginning, running test chips, running your test structures, and the whole development process starts from scratch.”
What has been LWLG’s role in this process and have they, in fact, facilitated solutions and worked passed these hurdles. LWLG’s E-O polymer modulators are compatible in Silicon, InP and GaAs foundries, although silicon offers the best opportunities to scale volume quickly and efficiently. The company is partnering with multiple foundries, packaging partners and module/transceiver partners to position LWLG for future high-volume production. They are also partnering to qualify polymer Process Development Kits (PDKs) with foundries using standard CMOS fabrication techniques. These deep activities with foundries for volume scaling appear to be bearing fruit as LWLG’s polymer slot modulator is in a CMOS/silicon compatible PDK.
Some wait with bated breath and the expectation that the answers will shortly be forthcoming, some just wait patiently .
