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Re: Lewrock post# 92109

Sunday, 01/30/2022 1:31:10 PM

Sunday, January 30, 2022 1:31:10 PM

Post# of 195876
You have grossly overestimated wafer lot throughput time on 10nm geometries or less, even with many layers. Throughput on larger geometries and fewer layers is even less.

And what makes you think adding a photonics component would reduce throughput? That isn't rational.
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