Saturday, July 31, 2021 8:42:21 PM
Respectfully, you might be under estimating LWLG who "is leading the high speed low power club" and its CEO Michael Lebby. when it comes to patents. Lightwave Logic is basically the pioneer in the photonics field and has outlasted huge names in the tech industry to get where Mr. Lebby has stated, we have "freedom of manufacturing". You want patents? I invite you to scroll down to the bottom and notice whose name is affiliated with each patent. This company knows what they are doing and this will be manifest in the coming months:
Patents by Inventor Michael Lebby
Michael Lebby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Guide transition device and method
Patent number: 11067748
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: November 8, 2019
Date of Patent: July 20, 2021
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger, Richard Becker
III-N to rare earth transition in a semiconductor structure
Patent number: 11063114
Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
Type: Grant
Filed: November 19, 2019
Date of Patent: July 13, 2021
Assignee: IQE plc
Inventors: Rytis Dargis, Andrew Clark, Rodney Pelzel, Michael Lebby, Robert Yanka
Direct drive region-less polymer modulator methods of fabricating and materials therefor
Patent number: 11042051
Abstract: A direct-drive region-less polymer modulator includes a waveguide having a first cladding layer, a passive core with a surface abutting the first cladding layer, the passive core extending to an optical input and an optical output. A shaped electro-optic polymer active component with a surface abutting the passive core region, the shaped component being polled to align dipoles and promote modulation of light and having a length that extends only within a modulation area defined by modulation electrodes. A second cladding layer enclosing the shaped component and designed to produce adiabatic transition of light waves traveling in the passive core region into the shaped component to travel the length of the shaped component and return to the passive core region. A portion of the multilayer waveguide defining the polymer modulator as a direct-drive polymer modulator.
Type: Grant
Filed: February 11, 2020
Date of Patent: June 22, 2021
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami
ACTIVE REGION-LESS MODULATOR AND METHOD
Publication number: 20210141250
Abstract: A polymer modulator includes a first cladding layer, a passive core region with a surface abutting a surface of the first cladding layer, the passive core region extending to define an optical input and an optical output for the modulator, a shaped electro-optic polymer active component with a surface abutting a surface of a central portion of the passive core region, the shaped electro-optic polymer active component being polled to align dipoles and promote modulation of light, the shaped electro-optic polymer active component having a length that extends only within a modulation area defined by modulation electrodes, and a second cladding layer enclosing the shaped electro-optic polymer active component and designed to produce adiabatic transition of light waves traveling in the passive core region into the shaped electro-optic polymer active component to travel the length of the shaped electro-optic polymer active component and return to the passive core region.
Type: Application
Filed: November 12, 2019
Publication date: May 13, 2021
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami, Zhiming Liu
ACTIVE REGION-LESS MODULATOR AND METHOD
Publication number: 20210141251
Abstract: A polymer modulator including a waveguide core defined over an insulating layer and having a first passive region including a light input, a second passive region including a light output, and an active region optically coupling the passive regions into a continuous waveguide core between the input and output. The waveguide core in the first and second passive regions including one of sol-gel and SiO2 surrounded by cladding including one of sol-gel and SiO2. The cladding in the passive regions having a first refractive index, the waveguide core in both regions having a second refractive index at least 0.01 higher than the first refractive index. The waveguide core in the active region including sol-gel, a cladding layer of sol-gel positioned between the insulating layer and the waveguide core, the refractive index of the waveguide core is at least 0.01 higher than the refractive index of the cladding layer.
Type: Application
Filed: May 5, 2020
Publication date: May 13, 2021
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Zhiming Liu
Protection layers for polymer modulators/waveguides
Patent number: 10989871
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Grant
Filed: November 21, 2019
Date of Patent: April 27, 2021
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
ELECTRONIC DEVICE WITH 2-DIMENSIONAL ELECTRON GAS BETWEEN POLAR-ORIENTED RARE-EARTH OXIDE LAYER GROWN OVER A SEMICONDUCTOR
Publication number: 20210005720
Abstract: Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.
Type: Application
Filed: February 15, 2019
Publication date: January 7, 2021
Inventors: Rytis Dargis, Andrew Clark, Richard Hammond, Rodney Pelzel, Michael Lebby
Hermetic capsule and method
Patent number: 10886694
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Grant
Filed: December 15, 2019
Date of Patent: January 5, 2021
Assignee: Lightwave Logic Inc.
Inventor: Michael Lebby
Integrated epitaxial metal electrodes
Patent number: 10825912
Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer.
Type: Grant
Filed: November 1, 2018
Date of Patent: November 3, 2020
Assignee: IQE plc
Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
DIRECT DRIVE REGION-LESS POLYMER MODULATOR METHODS OF FABRICATING AND MATERIALS THEREFOR
Publication number: 20200285085
Abstract: A direct-drive region-less polymer modulator includes a waveguide having a first cladding layer, a passive core with a surface abutting the first cladding layer, the passive core extending to an optical input and an optical output. A shaped electro-optic polymer active component with a surface abutting the passive core region, the shaped component being polled to align dipoles and promote modulation of light and having a length that extends only within a modulation area defined by modulation electrodes. A second cladding layer enclosing the shaped component and designed to produce adiabatic transition of light waves traveling in the passive core region into the shaped component to travel the length of the shaped component and return to the passive core region. A portion of the multilayer waveguide defining the polymer modulator as a direct-drive polymer modulator.
Type: Application
Filed: February 11, 2020
Publication date: September 10, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami
Fabrication process of polymer based photonic apparatus and the apparatus
Patent number: 10754093
Abstract: A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.
Type: Grant
Filed: May 14, 2019
Date of Patent: August 25, 2020
Assignee: Lightwave Logic Inc.
Inventors: Zhiming Liu, Michael Lebby, Brian Shaw, Richard Becker, Youngwoo Yi
ACTIVE REGION-LESS POLYMER MODULATOR INTEGRATED ON A COMMON PIC PLATFORM AND METHOD
Publication number: 20200183201
Abstract: A monolithic PIC including a monolithic laser formed in/on a platform and a polymer modulator monolithically built onto the platform and optically coupled to the laser. The modulator includes a first cladding layer, a passive core region with a surface abutting a surface of the first cladding layer, the core region extending to define an input and an output for the modulator. A shaped electro-optic polymer active component has a surface abutting a surface of a central portion of the core region. The active component is polled to align dipoles and promote modulation of light and has a length that extends only within a modulation area defined by modulation electrodes. A second cladding layer encloses the active component and is designed to produce adiabatic transition of light waves traveling in the core region into the active component to travel the length thereof and return to the core region.
Type: Application
Filed: December 11, 2019
Publication date: June 11, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami
III-N TO RARE EARTH TRANSITION IN A SEMICONDUCTOR STRUCTURE
Publication number: 20200161417
Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
Type: Application
Filed: November 19, 2019
Publication date: May 21, 2020
Inventors: Rytis Dargis, Andrew Clark, Rodney Pelzel, Michael Lebby, Robert Yanka
CONDUCTIVE MULTI-FIBER/PORT HERMETIC CAPSULE AND METHOD
Publication number: 20200150363
Abstract: A conductive hermetically sealed monolithic photonic integrated circuit with optical components and multiple optical and electrical inputs/outputs includes a semiconductor/metal base having sensitive components with multiple optical and electrical inputs, multiple optical and electrical outputs, and/or multiple optical and electrical inputs and outputs. An electrically conductive basic lid includes at least two of metal, dielectric and semiconductor materials combined to form an electrically conductive protective circuit. The conductive basic lid is sealed to the semiconductor/metal base by metallization so as to form a chamber including the sensitive components and hermetically sealing the chamber and the sensitive component from the ambient in a basic hermetic capsule and the electrically conductive protective circuit is formed and connected to protect the sensitive components from external electrical interference.
Type: Application
Filed: November 9, 2018
Publication date: May 14, 2020
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
HERMETIC CAPSULE AND METHOD
Publication number: 20200119516
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Application
Filed: December 15, 2019
Publication date: April 16, 2020
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
Pnictide buffer structures and devices for GaN base applications
Patent number: 10615141
Abstract: A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
Type: Grant
Filed: June 2, 2017
Date of Patent: April 7, 2020
Assignee: IQE plc
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Re-based integrated photonic and electronic layered structures
Patent number: 10605987
Abstract: Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
Type: Grant
Filed: January 18, 2019
Date of Patent: March 31, 2020
Assignee: IQE plc
Inventors: Andrew Clark, Rich Hammond, Rytis Dargis, Michael Lebby, Rodney Pelzel
GUIDE TRANSITION DEVICE AND METHOD
Publication number: 20200088939
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 8, 2019
Publication date: March 19, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J. Leonberger, Richard Becker
PROTECTION LAYERS FOR POLYMER MODULATORS/WAVEGUIDES
Publication number: 20200088941
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Application
Filed: November 21, 2019
Publication date: March 19, 2020
Applicant: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Direct-drive polymer modulator methods of fabricating and materials therefor
Patent number: 10591755
Abstract: A direct-drive polymer modulator including a platform, a multilayer waveguide formed in/on the platform, the waveguide including a bottom cladding layer, an electro-optic polymer core and a top cladding layer, and at least a portion of the waveguide forming a direct-drive polymer modulator.
Type: Grant
Filed: February 19, 2018
Date of Patent: March 17, 2020
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Frederick J Leonberger, Michael Lebby
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20200083668
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 11, 2019
Publication date: March 12, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Epitaxial AIN/cREO structure for RF filter applications
Patent number: 10573686
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Grant
Filed: June 19, 2017
Date of Patent: February 25, 2020
Assignee: IQE plc
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Hermetic capsule and method for a monolithic photonic integrated circuit
Patent number: 10574025
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Grant
Filed: January 26, 2018
Date of Patent: February 25, 2020
Assignee: Lightwave Logic Inc.
Inventor: Michael Lebby
Layer structures for RF filters fabricated using rare earth oxides and epitaxial aluminum nitride
Patent number: 10566944
Abstract: Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure can include an epitaxial crystalline rare earth oxide (REO) layer over a substrate, a first epitaxial electrode layer over the crystalline REO layer, and an epitaxial piezoelectric layer over the first epitaxial electrode layer. The layer structure can further include a second electrode layer over the epitaxial piezoelectric layer. The first electrode layer can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
Type: Grant
Filed: September 10, 2018
Date of Patent: February 18, 2020
Assignee: IQE plc
Inventors: Rodney Pelzel, Rytis Dargis, Andrew Clark, Howard Williams, Patrick Chin, Michael Lebby
Polymer modulator and laser integrated on a common platform and method
Patent number: 10527786
Abstract: A monolithic photonic integrated circuit includes a platform, a monolithic laser formed in/on the platform, and an electro-optic polymer modulator monolithically built onto the platform and optically coupled to the monolithic laser. The polymer modulator is optically coupled to the monolithic laser by waveguides including electro-optic polymer waveguides. The electro-optic polymer modulator and the electro-optic polymer waveguides including an electro-optic polymer core and top and bottom electro-optic polymer cladding layers. The electro-optic polymer core having an electro-optic coefficient (r33) greater than 250 pm/v, and a Tg 150° C. to 200° C., and the top and bottom electro-optic polymer cladding layers having a Tg approximately the same as the Tg of the electro-optic polymer core.
Type: Grant
Filed: August 31, 2017
Date of Patent: January 7, 2020
Assignee: Lightwave Logic Inc.
Inventors: Frederick J Leonberger, Michael Lebby, Richard Becker
Protection layers for polymer modulators/waveguides
Patent number: 10520673
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Grant
Filed: December 28, 2017
Date of Patent: December 31, 2019
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Guide transition device and method
Patent number: 10509164
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: September 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger, Richard Becker
Guide transition device with digital grating deflectors and method
Patent number: 10511146
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: November 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
FABRICATION PROCESS OF POLYMER BASED PHOTONIC APPARATUS AND THE APPARTUS
Publication number: 20190353843
Abstract: A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.
Type: Application
Filed: May 14, 2019
Publication date: November 21, 2019
Applicant: Lightwave Logic Inc.
Inventors: Zhiming Liu, Michael Lebby, Brian Shaw, Richard Becker, Youngwoo Yi
EPITAXIAL AIN/cREO STRUCTURE FOR RF FILTER APPLICATIONS
Publication number: 20190305039
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Application
Filed: June 19, 2017
Publication date: October 3, 2019
Applicant: IQE plc.
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
EMBEDDED HERMETIC CAPSULE AND METHOD
Publication number: 20190278036
Abstract: An embedded hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal embedded lid. The semiconductor/metal embedded lid sealed to the semiconductor/metal base by metallization so as to form a chamber including at least one of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient in an embedded hermetic capsule. External access to the sensitive semiconductor/polymer electrical and optical components is provided through the metallization.
Type: Application
Filed: March 7, 2018
Publication date: September 12, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
HERMETIC CAPSULE AND METHOD
Publication number: 20190237930
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Application
Filed: January 26, 2018
Publication date: August 1, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
RE-based Integrated Photonic and Electronic Layered Structures
Publication number: 20190227233
Abstract: Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
Type: Application
Filed: January 18, 2019
Publication date: July 25, 2019
Inventors: Andrew Clark, Rich Hammond, Rytis Dargis, Michael Lebby, Rodney Pelzel
POROUS DISTRIBUTED BRAGG REFLECTORS FOR LASER APPLICATIONS
Publication number: 20190221993
Abstract: Embodiments described herein provide a layered structure that comprises a substrate that includes a first porous multilayer of a first porosity, an active quantum well capping layer epitaxially grown over the first porous multilayer, and a second porous multilayer of the first porosity over the active quantum well capping layer, where the second porous multilayer aligns with the first porous multilayer.
Type: Application
Filed: January 18, 2019
Publication date: July 18, 2019
Inventors: Rich Hammond, Rodney Pelzel, Drew Nelson, Andrew Clark, David Cheskis, Michael Lebby
PROTECTION LAYERS FOR POLYMER MODULATORS/WAVEGUIDES
Publication number: 20190204506
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Application
Filed: December 28, 2017
Publication date: July 4, 2019
Applicant: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Rare earth pnictides for strain management
Patent number: 10332857
Abstract: Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.
Type: Grant
Filed: June 2, 2017
Date of Patent: June 25, 2019
Assignee: IQE plc
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Integrated Epitaxial Metal Electrodes
Publication number: 20190172923
Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.
Type: Application
Filed: January 25, 2019
Publication date: June 6, 2019
Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20190148913
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 14, 2017
Publication date: May 16, 2019
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Pnictide Buffer Structures and Devices for GaN Base Applications
Publication number: 20190139761
Abstract: A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
Type: Application
Filed: June 2, 2017
Publication date: May 9, 2019
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
GROUP III SEMICONDUCTOR EPITAXY FORMED ON SILICON VIA SINGLE CRYSTAL REN AND REO BUFFER LAYERS
Publication number: 20190122885
Abstract: Layer structures are described for the formation of Group III-V semiconductor material over Si<110> and Si<100>. Various buffer layers and interfaces reduce the lattice strain between the Group III-V semiconductor material and the Si<110> or Si<100> layers, allowing for the epitaxial formation of high quality Group III-V semiconductor material.
Type: Application
Filed: April 10, 2017
Publication date: April 25, 2019
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby, Rodney Pelzel
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20200083668
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 11, 2019
Publication date: March 12, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Epitaxial AIN/cREO structure for RF filter applications
Patent number: 10573686
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Grant
Filed: June 19, 2017
Date of Patent: February 25, 2020
Assignee: IQE plc
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Hermetic capsule and method for a monolithic photonic integrated circuit
Patent number: 10574025
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Grant
Filed: January 26, 2018
Date of Patent: February 25, 2020
Assignee: Lightwave Logic Inc.
Inventor: Michael Lebby
Layer structures for RF filters fabricated using rare earth oxides and epitaxial aluminum nitride
Patent number: 10566944
Abstract: Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure can include an epitaxial crystalline rare earth oxide (REO) layer over a substrate, a first epitaxial electrode layer over the crystalline REO layer, and an epitaxial piezoelectric layer over the first epitaxial electrode layer. The layer structure can further include a second electrode layer over the epitaxial piezoelectric layer. The first electrode layer can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
Type: Grant
Filed: September 10, 2018
Date of Patent: February 18, 2020
Assignee: IQE plc
Inventors: Rodney Pelzel, Rytis Dargis, Andrew Clark, Howard Williams, Patrick Chin, Michael Lebby
Polymer modulator and laser integrated on a common platform and method
Patent number: 10527786
Abstract: A monolithic photonic integrated circuit includes a platform, a monolithic laser formed in/on the platform, and an electro-optic polymer modulator monolithically built onto the platform and optically coupled to the monolithic laser. The polymer modulator is optically coupled to the monolithic laser by waveguides including electro-optic polymer waveguides. The electro-optic polymer modulator and the electro-optic polymer waveguides including an electro-optic polymer core and top and bottom electro-optic polymer cladding layers. The electro-optic polymer core having an electro-optic coefficient (r33) greater than 250 pm/v, and a Tg 150° C. to 200° C., and the top and bottom electro-optic polymer cladding layers having a Tg approximately the same as the Tg of the electro-optic polymer core.
Type: Grant
Filed: August 31, 2017
Date of Patent: January 7, 2020
Assignee: Lightwave Logic Inc.
Inventors: Frederick J Leonberger, Michael Lebby, Richard Becker
Protection layers for polymer modulators/waveguides
Patent number: 10520673
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Grant
Filed: December 28, 2017
Date of Patent: December 31, 2019
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Guide transition device and method
Patent number: 10509164
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: September 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger, Richard Becker
Guide transition device with digital grating deflectors and method
Patent number: 10511146
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: November 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
FABRICATION PROCESS OF POLYMER BASED PHOTONIC APPARATUS AND THE APPARTUS
Publication number: 20190353843
Abstract: A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.
Type: Application
Filed: May 14, 2019
Publication date: November 21, 2019
Applicant: Lightwave Logic Inc.
Inventors: Zhiming Liu, Michael Lebby, Brian Shaw, Richard Becker, Youngwoo Yi
EPITAXIAL AIN/cREO STRUCTURE FOR RF FILTER APPLICATIONS
Publication number: 20190305039
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Application
Filed: June 19, 2017
Publication date: October 3, 2019
Applicant: IQE plc.
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
EMBEDDED HERMETIC CAPSULE AND METHOD
Publication number: 20190278036
Abstract: An embedded hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal embedded lid. The semiconductor/metal embedded lid sealed to the semiconductor/metal base by metallization so as to form a chamber including at least one of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient in an embedded hermetic capsule. External access to the sensitive semiconductor/polymer electrical and optical components is provided through the metallization.
Type: Application
Filed: March 7, 2018
Publication date: September 12, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
HERMETIC CAPSULE AND METHOD
Publication number: 20190237930
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Application
Filed: January 26, 2018
Publication date: August 1, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
RE-based Integrated Photonic and Electronic Layered Structures
Publication number: 20190227233
Abstract: Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
Type: Application
Filed: January 18, 2019
Publication date: July 25, 2019
Inventors: Andrew Clark, Rich Hammond, Rytis Dargis, Michael Lebby, Rodney Pelzel
POROUS DISTRIBUTED BRAGG REFLECTORS FOR LASER APPLICATIONS
Publication number: 20190221993
Abstract: Embodiments described herein provide a layered structure that comprises a substrate that includes a first porous multilayer of a first porosity, an active quantum well capping layer epitaxially grown over the first porous multilayer, and a second porous multilayer of the first porosity over the active quantum well capping layer, where the second porous multilayer aligns with the first porous multilayer.
Type: Application
Filed: January 18, 2019
Publication date: July 18, 2019
Inventors: Rich Hammond, Rodney Pelzel, Drew Nelson, Andrew Clark, David Cheskis, Michael Lebby
PROTECTION LAYERS FOR POLYMER MODULATORS/WAVEGUIDES
Publication number: 20190204506
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Application
Filed: December 28, 2017
Publication date: July 4, 2019
Applicant: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Rare earth pnictides for strain management
Patent number: 10332857
Abstract: Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.
Type: Grant
Filed: June 2, 2017
Date of Patent: June 25, 2019
Assignee: IQE plc
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Integrated Epitaxial Metal Electrodes
Publication number: 20190172923
Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.
Type: Application
Filed: January 25, 2019
Publication date: June 6, 2019
Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20190148913
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 14, 2017
Publication date: May 16, 2019
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Pnictide Buffer Structures and Devices for GaN Base Applications
Publication number: 20190139761
Abstract: A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
Type: Application
Filed: June 2, 2017
Publication date: May 9, 2019
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
GROUP III SEMICONDUCTOR EPITAXY FORMED ON SILICON VIA SINGLE CRYSTAL REN AND REO BUFFER LAYERS
Publication number: 20190122885
Abstract: Layer structures are described for the formation of Group III-V semiconductor material over Si<110> and Si<100>. Various buffer layers and interfaces reduce the lattice strain between the Group III-V semiconductor material and the Si<110> or Si<100> layers, allowing for the epitaxial formation of high quality Group III-V semiconductor material.
Type: Application
Filed: April 10, 2017
Publication date: April 25, 2019
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby, Rodney Pelzel
REO gate dielectric for III-N device on Si substrate
Patent number: 8878188
Abstract: A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material.
Type: Grant
Filed: February 22, 2013
Date of Patent: November 4, 2014
Assignee: Translucent, Inc.
Inventors: Rytis Dargis, Robin Smith, Andrew Clark, Erdem Arkun, Michael Lebby
AlN cap grown on GaN/REO/silicon substrate structure
Patent number: 8872308
Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
Type: Grant
Filed: February 20, 2013
Date of Patent: October 28, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
IIIONon single crystal SOI substrate and III n growth platform
Patent number: 8835955
Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
Type: Grant
Filed: August 30, 2011
Date of Patent: September 16, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Rytis Dargis, Andrew Clark, Michael Lebby
REO/ALO/A1N template for III-N material growth on silicon
Patent number: 8823055
Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.
Type: Grant
Filed: December 17, 2012
Date of Patent: September 2, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
III-N material grown on AIO/AIN buffer on Si substrate
Patent number: 8823025
Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Grant
Filed: February 20, 2013
Date of Patent: September 2, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE
Publication number: 20140239307
Abstract: A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material.
Type: Application
Filed: February 22, 2013
Publication date: August 28, 2014
Inventors: RYTIS DARGIS, ROBIN SMITH, ANDREW CLARK, ERDEM ARKUN, MICHAEL LEBBY
AlN CAP GROWN ON GaN/REO/SILICON SUBSTRATE STRUCTURE
Publication number: 20140231818
Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
Type: Application
Filed: February 20, 2013
Publication date: August 21, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
III-N MATERIAL GROWN ON ALO/ALN BUFFER ON SI SUBSTRATE
Publication number: 20140231817
Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Application
Filed: February 20, 2013
Publication date: August 21, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON
Publication number: 20140225123
Abstract: A III-N template formed on a silicon substrate includes a Distributed Bragg Reflector positioned on the silicon substrate. The Distributed Bragg Reflector is substantially crystal lattice matched to the surface of the silicon substrate. An aluminum oxide layer is positioned on the surface of the Distributed Bragg Reflector and substantially crystal lattice matched to the surface of the Distributed Bragg Reflector. A layer of aluminum nitride (AlN) is positioned on the surface of the aluminum oxide layer and substantially crystal lattice matched to the surface of the aluminum oxide layer. A III-N LED structure including at least one III-N layer can then be grown on the aluminum nitride layer and substantially crystal lattice matched to the surface of the aluminum nitride layer.
Type: Application
Filed: February 13, 2014
Publication date: August 14, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
Laser cooling of modified SOI wafer
Patent number: 8794010
Abstract: A laser cooling system includes a substrate, an REO layer of single crystal rare earth oxide including at least one rare earth element positioned on the surface of the substrate, and an active layer of single crystal semiconductor material positioned on the REO layer to form a semiconductor-on-insulator (SOI) device. Light guiding structure is at least partially formed by the REO layer so as to introduce energy elements into the REO layer and produce cooling by anti-Stokes fluorescence. The active layer of single crystal semiconductor material is positioned on the REO layer in proximity to the light guiding structure so as to receive the cooling.
Type: Grant
Filed: December 13, 2010
Date of Patent: August 5, 2014
Assignee: Translucent, Inc.
Inventors: David L. Williams, Andrew Clark, Michael Lebby
REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON
Publication number: 20140167057
Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.
Type: Application
Filed: December 17, 2012
Publication date: June 19, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
Re-silicide gate electrode for III-N device on Si substrate
Patent number: 8748900
Abstract: A method of fabricating a rare earth silicide gate electrode on III-N material grown on a silicon substrate includes growing a single crystal stress compensating template on a silicon substrate. The template is substantially crystal lattice matched to the surface of the silicon substrate. A single crystal GaN structure is grown on the surface of the template and substantially crystal lattice matched to the template. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched to the GaN structure. A single crystal monoclinic rare earth oxide dielectric layer is grown on the active layer of III-N material and a single crystal rare earth silicide gate electrode is grown on the dielectric layer, the silicide. Relative portions of the gadolinium metal and the silicon are adjusted during deposition so they react to form rare earth silicide during deposition.
Type: Grant
Filed: March 27, 2013
Date of Patent: June 10, 2014
Assignee: Translucent, Inc.
Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun, Robin Smith, Michael Lebby
A1N inter-layers in III-N material grown on DBR/silicon substrate
Patent number: 8680507
Abstract: A DBR/gallium nitride/aluminum nitride base grown on a silicon substrate includes a Distributed Bragg Reflector (DBR) positioned on the silicon substrate. The DBR is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the DBR, an inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Grant
Filed: January 16, 2013
Date of Patent: March 25, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
DELTA DOPING AT Si-Ge INTERFACE
Publication number: 20140077339
Abstract: A IV or III-V device is fabricated on a germanium template on a silicon substrate and includes a thin layer of Ge epitaxially grown on a silicon substrate. The thin layer includes Ge delta doped with Sn at the silicon substrate. A single crystal layer of Ge is epitaxially grown on the thin layer of Ge doped with Sn. A structure including one of IV material and III-V material is epitaxially grown on the single crystal layer of Ge.
Type: Application
Filed: September 14, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
Si-Ge-Sn ON REO TEMPLATE
Publication number: 20140077338
Abstract: An electronic device includes IV material grown on a silicon substrate. The device includes a crystalline silicon substrate and a rare earth structure epitaxially grown on the silicon substrate. The rare earth structure includes a layer of a rare earth oxide with electrical insulating characteristics so that the rare earth structure provides electrical insulation from the silicon substrate. A single crystal IV material film is epitaxially grown on the rare earth structure. The single crystal IV material film includes one of crystal lattice matching or crystal lattice mismatching the IV material film to the rare earth structure.
Type: Application
Filed: September 14, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
IV MATERIAL PHOTONIC DEVICE ON DBR
Publication number: 20140077240
Abstract: A photonic structure including a substrate of either crystalline silicon or germanium and a multilayer distributed Bragg reflector (DBR) positioned on the substrate. The DBR includes material substantially crystal lattice matching the DBR to the substrate. The DBR includes a plurality of pairs of layers of material including any combination of IV materials and any rare earth oxide (REO). A photonic device including multilayers of single crystal IV material positioned on the DBR and including material substantially crystal lattice matching the DBR to the photonic device.
Type: Application
Filed: September 17, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans, Andrew Clark
III-V SEMICONDUCTOR INTERFACE WITH GRADED GeSn ON SILICON
Publication number: 20140076390
Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
Type: Application
Filed: September 14, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
GRADED GeSn ON SILICON
Publication number: 20140053894
Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.
Type: Application
Filed: August 23, 2012
Publication date: February 27, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
Solar cells with engineered spectral conversion
Patent number: 8637763
Abstract: A solar cell with engineered spectral conversion elements or components includes a single crystal silicon solar cell having a back surface. At least one spectral conversion element is formed on the back surface. The conversion element includes single crystal rare earth oxide, and the single crystal rare earth oxide is crystal lattice matched to the back surface of the silicon solar cell. Material including silicon is formed on the back surface in a surrounding and embedding relationship to the at least one spectral conversion element. A back reflector is positioned on the material formed on the back surface so as to reflect light passing through the silicon formed on the back surface.
Type: Grant
Filed: May 26, 2010
Date of Patent: January 28, 2014
Assignee: Translucent, Inc.
Inventors: Michael Lebby, Andrew Clark
Oxygen engineered single-crystal REO template
Patent number: 8636844
Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
Type: Grant
Filed: July 6, 2012
Date of Patent: January 28, 2014
Assignee: Translucent, Inc.
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
AlN inter-layers in III-N material grown on REO/silicon substrate
Patent number: 8633569
Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Grant
Filed: January 16, 2013
Date of Patent: January 21, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
OXYGEN ENGINEERED SINGLE-CRYSTAL REO TEMPLATE
Publication number: 20140008644
Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
Type: Application
Filed: July 6, 2012
Publication date: January 9, 2014
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
Silicon, aluminum oxide, aluminum nitride template for optoelectronic and power devices
Patent number: 8623747
Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes forming an aluminum oxide coating on the surface of the silicon substrate, the aluminum oxide being substantially crystal lattice matched to the surface of the silicon substrate and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide coating substantially crystal lattice matched to the surface of the aluminum nitride.
Type: Grant
Filed: December 17, 2012
Date of Patent: January 7, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark
SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx
Publication number: 20130334536
Abstract: A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide.
Type: Application
Filed: February 20, 2013
Publication date: December 19, 2013
Inventors: Rytis Dargis, Andrew Clark, Robin Smith, Michael Lebby
Integrated pump laser and rare earth waveguide amplifier
Patent number: 8559097
Abstract: A light amplifier includes a single crystal semiconductor substrate with a rare earth oxide, light amplifying gain medium deposited on the substrate and formed into a light waveguide, and a pump laser. A lattice matching virtual substrate integrates the pump laser to the gain medium with a first opposed surface crystal lattice matched to the gain medium and second opposed surface crystal lattice matched to the pump laser. The pump laser is positioned with a light output surface coupled to a light input surface of the gain medium so as to introduce pump energy into the light waveguide. The light amplifier has a very small footprint and allows the integration of control and monitoring electronics.
Type: Grant
Filed: July 21, 2010
Date of Patent: October 15, 2013
Assignee: Translucent, Inc.
Inventors: David L. Williams, Andrew Clark, Michael Lebby
Integrated rare earth devices
Patent number: 8553741
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Grant
Filed: November 12, 2012
Date of Patent: October 8, 2013
Assignee: Translucent Inc.
Inventor: Michael Lebby
NUCLEATION OF III-N ON REO TEMPLATES
Publication number: 20130248853
Abstract: A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.
Type: Application
Filed: March 18, 2013
Publication date: September 26, 2013
Inventors: Erdem Arkun, Andrew Clark, Rytis Dargis, Radek Roucka, Michael Lebby
III-N ON SILICON USING NANO STRUCTURED INTERFACE LAYER
Publication number: 20130214282
Abstract: A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent.
Type: Application
Filed: February 17, 2012
Publication date: August 22, 2013
Inventors: Erdem Arkun, Radek Roucka, Andrew Clark, Robin Smith, Michael Lebby
Modification of REO by subsequent III-N EPI process
Patent number: 8501635
Abstract: A method of growing single crystal III-N material on a semiconductor substrate includes providing a substrate including one of crystalline silicon or germanium and a layer of rare earth oxide. A layer of single crystal III-N material is epitaxially grown on the substrate using a process that elevates the temperature of the layer of rare earth oxide into a range of approximately 750° C. to approximately 1250° C. in the presence of an N or a III containing species, whereby a portion of the layer of rare earth oxide is transformed to a new alloy.
Type: Grant
Filed: September 29, 2012
Date of Patent: August 6, 2013
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Rytis Dargis, Erdem Arkun, Michael Lebby
REO-Si TEMPLATE WITH INTEGRATED REO LAYERS FOR LIGHT EMISSION
Publication number: 20130153918
Abstract: A III-N on silicon LED constructed to emit light in the visible range includes a layer of single crystal III-N with a light emitting diode formed therein and designed to emit light at a first wavelength through a lower surface, a REO-Si template mated to the layer of single crystal III-N and designed to approximately crystal lattice match a silicon substrate, and a light emission layer of rare earth oxide selected to receive and absorb light at the first wavelength, up-convert the absorbed light, and re-emit light at a second wavelength in the visible range. The lower surface of the REO-Si template is either mated to the upper surface of a crystalline silicon substrate with the light emission layer integrated into the REO-Si template or mated to an upper surface of the light emission layer with a lower surface of the light emission layer mated to the crystalline silicon substrate.
Type: Application
Filed: December 16, 2011
Publication date: June 20, 2013
Inventors: Andrew Clark, Michael Lebby
High efficiency solar cell using IIIB material transition layers
Patent number: 8455756
Abstract: A solar cell including a base of single crystal silicon with a cubic crystal structure and a single crystal layer of a second material with a higher bandgap than the bandgap of silicon. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the base and the layer of second material with the one surface lattice matched to the base and the opposed surface lattice matched to the layer of second material.
Type: Grant
Filed: February 19, 2010
Date of Patent: June 4, 2013
Assignee: Translucent, Inc.
Inventors: Michael Lebby, Andrew Clark
STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON
Publication number: 20130099357
Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
Type: Application
Filed: October 21, 2011
Publication date: April 25, 2013
Inventors: Rytis Dargis, Erdem Arkun, Radek Roucka, Andrew Clark, Michael Lebby
INTEGRATED RARE EARTH DEVICES
Publication number: 20130071960
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Application
Filed: November 12, 2012
Publication date: March 21, 2013
Inventor: MICHAEL LEBBY
LATTICE MATCHED CRYSTALLINE REFLECTOR
Publication number: 20130062610
Abstract: A virtual substrate structure with a lattice matched crystalline reflector for a light emitting device including a single crystal rare earth oxide layer deposited on a silicon substrate and substantially crystal lattice matched to the silicon substrate. A reflective layer of single crystal electrically conductive material is deposited on the layer of single crystal rare earth oxide and a layer of single crystal semiconductor material is positioned in overlying relationship to the reflective layer and substantially crystal lattice matched to the reflective layer. A single crystal rare earth oxide layer is optionally deposited between the reflective layer and the layer of semiconductor material.
Type: Application
Filed: September 14, 2011
Publication date: March 14, 2013
Inventors: Andrew Clark, Michael Lebby, Robin Smith, David Williams
III-N FET ON SILICON USING FIELD SUPPRESSING REO
Publication number: 20130062609
Abstract: A III-N on silicon substrate with enhanced breakdown voltage including a rare earth oxide structure deposited on the silicon substrate and a layer of single crystal III-N semiconductor material deposited on the rare earth oxide structure. The rare earth oxide has a dielectric constant greater (approximately twice) than the III-N semiconductor material. The rare earth oxide structure is selected to cooperate with the layer of single crystal III-N semiconductor material to reduce the thickness of the layer of single crystal III-N semiconductor material required for a selected breakdown voltage to a value less than a thickness of the layer of single crystal III-N semiconductor material for the selected breakdown voltage without the cooperating single crystal rare earth oxide.
Type: Application
Filed: September 14, 2011
Publication date: March 14, 2013
Inventors: Robin Smith, David Williams, Rytis Dargis, Michael Lebby
Single crystal reo buffer on amorphous SiO
Patent number: 8394194
Abstract: A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide.
Type: Grant
Filed: June 13, 2012
Date of Patent: March 12, 2013
Inventors: Rytis Dargis, Andrew Clark, Robin Smith, Michael Lebby
RARE EARTH OXY-NITRIDE BUFFERED III-N ON SILICON
Publication number: 20130032858
Abstract: Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer of single crystal rare earth oxy-nitride is deposited on the REO structure. The REO structure is stress engineered to approximately crystal lattice match the layer of rare earth oxy-nitride so as to provide a predetermined amount of stress in the layer of rare earth oxy-nitride. A III oxy-nitride structure, including several layers of single crystal rare earth oxy-nitride, is deposited on the layer of rare earth oxy-nitride. A layer of single crystal III-N nitride is deposited on the III oxy-nitride structure. The III oxy-nitride structure is chemically engineered to approximately crystal lattice match the layer of III-N nitride and to transfer the predetermined amount of stress in the layer of rare earth oxy-nitride to the layer of III-N nitride.
Type: Application
Filed: August 3, 2011
Publication date: February 7, 2013
Inventors: Andrew Clark, Erdem Arkun, Robin Smith, Michael Lebby
Spontaneous/stimulated light emitting ?-cavity device
Patent number: 8331410
Abstract: A light emitting device with a ?-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-? erbium dielectric provides a high gain ?-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation.
Type: Grant
Filed: December 10, 2009
Date of Patent: December 11, 2012
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Integrated rare earth devices
Patent number: 8331413
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Grant
Filed: February 4, 2010
Date of Patent: December 11, 2012
Inventor: Michael Lebby
Single Crystal Ge On Si
Publication number: 20120280276
Abstract: A single crystal germanium-on-silicon structure includes a single crystal silicon substrate. A single crystal layer of gadolinium oxide is epitaxially grown on the substrate. The gadolinium oxide has a cubic crystal structure and a lattice spacing approximately equal to the lattice spacing or a multiple of the single crystal silicon. A single crystal layer of lanthanum oxide is epitaxially grown on the gadolinium oxide with a thickness of approximately 12 nm or less. The lanthanum oxide has a lattice spacing approximately equal to the lattice spacing or a multiple of single crystal germanium and a cubic crystal structure approximately similar to the cubic crystal structure of the gadolinium oxide. A single crystal layer of germanium with a (111) crystal orientation is epitaxially grown on the layer of lanthanum oxide.
Type: Application
Filed: March 20, 2012
Publication date: November 8, 2012
Inventors: Rytis Dargis, Erdem Arkun, Andrew Clark, Michael Lebby
Multilayer Rare Earth Device
Publication number: 20120256232
Abstract: Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed.
Type: Application
Filed: September 30, 2011
Publication date: October 11, 2012
Applicant: Translucent, Inc.
Inventors: Andrew Clark, F. Erdem Arkun, Michael Lebby
HEXAGONAL REO TEMPLATE BUFFER FOR III-N LAYERS ON SILICON
Publication number: 20120183767
Abstract: A III-N on silicon structure including a substrate of single crystal silicon with a cubic crystal structure and a layer of single crystal III-N material. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the substrate and the layer of III-N material with the one surface lattice matched to the substrate and the opposed surface lattice matched to the layer of III-N material.
Type: Application
Filed: December 16, 2011
Publication date: July 19, 2012
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
LASER COOLING OF MODIFIED SOI WAFER
Publication number: 20120147906
Abstract: A laser cooling system includes a substrate, an REO layer of single crystal rare earth oxide including at least one rare earth element positioned on the surface of the substrate, and an active layer of single crystal semiconductor material positioned on the REO layer to form a semiconductor-on-insulator (SOI) device. Light guiding structure is at least partially formed by the REO layer so as to introduce energy elements into the REO layer and produce cooling by anti-Stokes fluorescence. The active layer of single crystal semiconductor material is positioned on the REO layer in proximity to the light guiding structure so as to receive the cooling.
Type: Application
Filed: December 13, 2010
Publication date: June 14, 2012
Inventors: David L. Williams, Andrew Clark, Michael Lebby
SOLAR CELLS WITH MAGNETICALLY ENHANCED UP-CONVERSION
Publication number: 20120145243
Abstract: A method of magnetically enhancing up-conversion components includes providing at least one of up-conversion material and sensitizer material (i.e. up-conversion components), generally in conjunction with a semiconductor solar cell, and positioning magnetic apparatus adjacent the up-conversion components to supply a magnetic field to the up-conversion components. The magnetic field has an intensity and direction selected to enhance operation of the up-conversion components.
Type: Application
Filed: December 10, 2010
Publication date: June 14, 2012
Inventors: David L. Williams, Andrew Clark, Michael Lebby
IIIOxNy ON REO/Si
Publication number: 20120104567
Abstract: An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A layer of single crystal IIIOxNy is formed in overlying relationship on the rare earth oxide by transitioning from the layer of rare earth oxide to a single crystal layer of IIIOxNy within a one wafer single epitaxial process. In the preferred embodiment the substrate is silicon, the rare earth oxide is Gd2O3, and the IIIOxNy includes AlOxNy.
Type: Application
Filed: August 12, 2011
Publication date: May 3, 2012
Inventors: Andrew Clark, Erdem Arkun, Michael Lebby
IIIOxNy ON SINGLE CRYSTAL SOI SUBSTRATE AND III n GROWTH PLATFORM
Publication number: 20120104443
Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
Type: Application
Filed: August 30, 2011
Publication date: May 3, 2012
Inventors: Andrew Clark, Michael Lebby, Erdem Arkun, Rytis Dargis
Photovoltaic conversion using rare earths plus Group IV Sensitizers
Publication number: 20120073648
Abstract: The invention relates to photovoltaic device structures of more than one layer comprising rare earth compounds and Group IV materials enabling spectral harvesting outside the conventional absorption limits for silicon.
Type: Application
Filed: September 24, 2010
Publication date: March 29, 2012
Inventors: Andrew Clark, Robin Smith, Scott Semans, F. Erdem Arkun, Michael Lebby
INTERGRATED PUMP LASER AND RARE EARTH WAVEGUIDE AMPLIFIER
Publication number: 20120019902
Abstract: A light amplifier includes a single crystal semiconductor substrate with a rare earth oxide, light amplifying gain medium deposited on the substrate and formed into a light waveguide, and a pump laser. A lattice matching virtual substrate integrates the pump laser to the gain medium with a first opposed surface crystal lattice matched to the gain medium and second opposed surface crystal lattice matched to the pump laser. The pump laser is positioned with a light output surface coupled to a light input surface of the gain medium so as to introduce pump energy into the light waveguide. The light amplifier has a very small footprint and allows the integration of control and monitoring electronics.
Type: Application
Filed: July 21, 2010
Publication date: January 26, 2012
Inventors: David L. Williams, Andrew Clark, Michael Lebby
SOLAR CELLS WITH ENGINEERED SPECTRAL CONVERSION
Publication number: 20110290313
Abstract: A solar cell with engineered spectral conversion elements or components includes a single crystal silicon solar cell having a back surface. At least one spectral conversion element is formed on the back surface. The conversion element includes single crystal rare earth oxide, and the single crystal rare earth oxide is crystal lattice matched to the back surface of the silicon solar cell. Material including silicon is formed on the back surface in a surrounding and embedding relationship to the at least one spectral conversion element. A back reflector is positioned on the material formed on the back surface so as to reflect light passing through the silicon formed on the back surface.
Type: Application
Filed: May 26, 2010
Publication date: December 1, 2011
Inventors: MICHAEL LEBBY, Andrew Clark
Multijunction rare earth solar cell
Patent number: 8049100
Abstract: Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed.
Type: Grant
Filed: November 16, 2009
Date of Patent: November 1, 2011
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Active rare earth tandem solar cell
Patent number: 8039738
Abstract: The use of rare-earth (RE and O, N, P) based materials to transition between two different semiconductor materials and enable up and/or down conversion of incident radiation is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacing enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds.
Type: Grant
Filed: November 16, 2009
Date of Patent: October 18, 2011
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Passive rare earth tandem solar cell
Patent number: 8039737
Abstract: The use of rare-earth (RE+O, N, P) based materials to transition between two semiconductor materials is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacings enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds. Disclosed embodiments include tandem solar cells.
Type: Grant
Filed: November 16, 2009
Date of Patent: October 18, 2011
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
ACTIVE SOLAR CONCENTRATOR WITH MULTI-JUNCTION DEVICES
Publication number: 20110220173
Abstract: An active solar concentrator including a horizontally oriented structure including light directing portions with partially reflective surfaces directing light vertically impinging thereon into a central area and a solar module positioned in the central area to receive light from the partially reflective surfaces. The light directing portions each including at least one layer of rare earth oxide designed to up-convert light passing therethrough and positioned to receive light directly and/or from an outer light directing portion. The solar module may include a plurality of multi junction solar cells formed on a common substrate.
Type: Application
Filed: March 9, 2010
Publication date: September 15, 2011
Inventor: MICHAEL LEBBY
HIGH EFFICIENCY SOLAR CELL USING IIIB MATERIAL TRANSITION LAYERS
Publication number: 20110203666
Abstract: A solar cell including a base of single crystal silicon with a cubic crystal structure and a single crystal layer of a second material with a higher bandgap than the bandgap of silicon. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the base and the layer of second material with the one surface lattice matched to the base and the opposed surface lattice matched to the layer of second material.
Type: Application
Filed: February 19, 2010
Publication date: August 25, 2011
Inventors: Michael Lebby, Andrew Clark
INTEGRATED RARE EARTH DEVICES
Publication number: 20110188533
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Application
Filed: February 4, 2010
Publication date: August 4, 2011
Inventor: MICHAEL LEBBY
Stacked transistors and process
Patent number: 7968384
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Grant
Filed: July 31, 2009
Date of Patent: June 28, 2011
Inventors: Petar B. Atanakovic, Michael Lebby
Full color display
Patent number: 7967653
Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Grant
Filed: September 28, 2009
Date of Patent: June 28, 2011
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
MULTILAYERED BOX IN FDSOI MOSFETS
Publication number: 20110108908
Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
Type: Application
Filed: September 29, 2010
Publication date: May 12, 2011
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Multilayered BOX in FDSOI MOSFETS
Patent number: 7821066
Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
Type: Grant
Filed: December 8, 2006
Date of Patent: October 26, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Passive Rare Earth Tandem Solar Cell
Publication number: 20100122720
Abstract: The use of rare-earth (RE+O, N, P) based materials to transition between two semiconductor materials is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacings enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds. Disclosed embodiments include tandem solar cells.
Type: Application
Filed: November 16, 2009
Publication date: May 20, 2010
Applicant: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Active rare earth tandem solar cell
Publication number: 20100116315
Abstract: The use of rare-earth (RE and O, N, P) based materials to transition between two different semiconductor materials and enable up and/or down conversion of incident radiation is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacing enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds.
Type: Application
Filed: November 16, 2009
Publication date: May 13, 2010
Applicant: TRANSLUCENT, INC.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Multijunction rare earth solar cell
Publication number: 20100109047
Abstract: Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed.
Type: Application
Filed: November 16, 2009
Publication date: May 6, 2010
Applicant: TRANSLUCENT, INC.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
FULL COLOR DISPLAY
Publication number: 20100112736
Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Application
Filed: September 28, 2009
Publication date: May 6, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
SPONTANEOUS/STIMULATED LIGHT EMITTING ?-CAVITY DEVICE
Publication number: 20100084680
Abstract: A light emitting device with a p-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-? erbium dielectric provides a high gain ?-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation.
Type: Application
Filed: December 10, 2009
Publication date: April 8, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Spontaneous/stimulated light emitting ?-cavity device
Patent number: 7643526
Abstract: A light emitting device with a ?-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-? erbium dielectric provides a high gain ?-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation.
Type: Grant
Filed: June 21, 2006
Date of Patent: January 5, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
STACKED TRANSISTORS AND PROCESS
Publication number: 20090291535
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Application
Filed: July 31, 2009
Publication date: November 26, 2009
Inventors: Petar B. Atanackovic, Michael Lebby
Full color display including LEDs with rare earth active areas and different radiative transistions
Patent number: 7605531
Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Grant
Filed: October 25, 2005
Date of Patent: October 20, 2009
Assignee: Translucent, Inc.
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Stacked transistors and process
Patent number: 7579623
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Grant
Filed: July 22, 2005
Date of Patent: August 25, 2009
Assignee: Translucent, Inc.
Inventors: Petar B. Atanackovic, Michael Lebby
Signal and/or ground planes with double buried insulator layers and fabrication process
Patent number: 7538016
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Grant
Filed: December 20, 2007
Date of Patent: May 26, 2009
Assignee: Translucent, Inc.
Inventors: Petar B. Atanakovic, Michael Lebby
Selective colored light emitting diode
Patent number: 7388230
Abstract: A selective colored LED includes a light emitting area epitaxially grown on a first cladding layer, and a second cladding layer epitaxially grown on the light emitting area. The light emitting area includes at least one thin single crystal layer of rare earth material having at least one radiative transition producing a radiation wavelength of a selected color. The first cladding layer is positioned on a first mirror stack, with pairs of mirrors having an effective thickness of at least one half wavelength of the selected color, and a second mirror stack is positioned on the second cladding layer. Generally, the color of the LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Grant
Filed: October 26, 2005
Date of Patent: June 17, 2008
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Multilayered box in FDSOI MOSFETS
Publication number: 20080135924
Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
Type: Application
Filed: December 8, 2006
Publication date: June 12, 2008
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Strain inducing multi-layer cap
Patent number: 7365357
Abstract: A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.
Type: Grant
Filed: July 22, 2005
Date of Patent: April 29, 2008
Assignee: Translucent Inc.
Inventors: Petar B. Atanackovic, Michael Lebby
SIGNAL AND/OR GROUND PLANES WITH DOUBLE BURIED INSULATOR LAYERS AND FABRICATION PROCESS
Publication number: 20080093670
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Application
Filed: December 20, 2007
Publication date: April 24, 2008
Applicant: TRANSLUCENT INC.
Inventors: Petar Atanakovic, MICHAEL LEBBY
IC on non-semiconductor substrate
Patent number: 7355269
Abstract: An integrated circuit and method of fabrication including a non-semiconductor material substrate with a layer of single crystal rare earth deposited on the surface thereof. A layer of single crystal semiconductor material is grown on the layer of single crystal rare earth and an integrated circuit is formed in the layer of single crystal semiconductor material. In a preferred embodiment the single crystal semiconductor material is silicon and the integrated circuit is formed by standard semiconductor industry processes.
Type: Grant
Filed: April 6, 2006
Date of Patent: April 8, 2008
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Signal and/or ground planes with double buried insulator layers and fabrication process
Patent number: 7323396
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Grant
Filed: April 29, 2005
Date of Patent: January 29, 2008
Assignee: Translucent Inc.
Inventors: Petar B. Atanackovic, Michael Lebby
Strain inducing multi-layer cap
Publication number: 20070018203
Abstract: A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.
Type: Application
Filed: July 22, 2005
Publication date: January 25, 2007
Inventors: Petar Atanackovic, Michael Lebby
Stacked transistors and process
Publication number: 20070018166
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Application
Filed: July 22, 2005
Publication date: January 25, 2007
Inventors: Petar Atanackovic, Michael Lebby
Signal and/or ground planes with double buried insulator layers and fabrication process
Publication number: 20060246691
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Application
Filed: April 29, 2005
Publication date: November 2, 2006
Inventors: Petar Atanackovic, Michael Lebby
Patents by Inventor Michael Lebby
Michael Lebby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Guide transition device and method
Patent number: 11067748
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: November 8, 2019
Date of Patent: July 20, 2021
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger, Richard Becker
III-N to rare earth transition in a semiconductor structure
Patent number: 11063114
Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
Type: Grant
Filed: November 19, 2019
Date of Patent: July 13, 2021
Assignee: IQE plc
Inventors: Rytis Dargis, Andrew Clark, Rodney Pelzel, Michael Lebby, Robert Yanka
Direct drive region-less polymer modulator methods of fabricating and materials therefor
Patent number: 11042051
Abstract: A direct-drive region-less polymer modulator includes a waveguide having a first cladding layer, a passive core with a surface abutting the first cladding layer, the passive core extending to an optical input and an optical output. A shaped electro-optic polymer active component with a surface abutting the passive core region, the shaped component being polled to align dipoles and promote modulation of light and having a length that extends only within a modulation area defined by modulation electrodes. A second cladding layer enclosing the shaped component and designed to produce adiabatic transition of light waves traveling in the passive core region into the shaped component to travel the length of the shaped component and return to the passive core region. A portion of the multilayer waveguide defining the polymer modulator as a direct-drive polymer modulator.
Type: Grant
Filed: February 11, 2020
Date of Patent: June 22, 2021
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami
ACTIVE REGION-LESS MODULATOR AND METHOD
Publication number: 20210141250
Abstract: A polymer modulator includes a first cladding layer, a passive core region with a surface abutting a surface of the first cladding layer, the passive core region extending to define an optical input and an optical output for the modulator, a shaped electro-optic polymer active component with a surface abutting a surface of a central portion of the passive core region, the shaped electro-optic polymer active component being polled to align dipoles and promote modulation of light, the shaped electro-optic polymer active component having a length that extends only within a modulation area defined by modulation electrodes, and a second cladding layer enclosing the shaped electro-optic polymer active component and designed to produce adiabatic transition of light waves traveling in the passive core region into the shaped electro-optic polymer active component to travel the length of the shaped electro-optic polymer active component and return to the passive core region.
Type: Application
Filed: November 12, 2019
Publication date: May 13, 2021
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami, Zhiming Liu
ACTIVE REGION-LESS MODULATOR AND METHOD
Publication number: 20210141251
Abstract: A polymer modulator including a waveguide core defined over an insulating layer and having a first passive region including a light input, a second passive region including a light output, and an active region optically coupling the passive regions into a continuous waveguide core between the input and output. The waveguide core in the first and second passive regions including one of sol-gel and SiO2 surrounded by cladding including one of sol-gel and SiO2. The cladding in the passive regions having a first refractive index, the waveguide core in both regions having a second refractive index at least 0.01 higher than the first refractive index. The waveguide core in the active region including sol-gel, a cladding layer of sol-gel positioned between the insulating layer and the waveguide core, the refractive index of the waveguide core is at least 0.01 higher than the refractive index of the cladding layer.
Type: Application
Filed: May 5, 2020
Publication date: May 13, 2021
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Zhiming Liu
Protection layers for polymer modulators/waveguides
Patent number: 10989871
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Grant
Filed: November 21, 2019
Date of Patent: April 27, 2021
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
ELECTRONIC DEVICE WITH 2-DIMENSIONAL ELECTRON GAS BETWEEN POLAR-ORIENTED RARE-EARTH OXIDE LAYER GROWN OVER A SEMICONDUCTOR
Publication number: 20210005720
Abstract: Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.
Type: Application
Filed: February 15, 2019
Publication date: January 7, 2021
Inventors: Rytis Dargis, Andrew Clark, Richard Hammond, Rodney Pelzel, Michael Lebby
Hermetic capsule and method
Patent number: 10886694
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Grant
Filed: December 15, 2019
Date of Patent: January 5, 2021
Assignee: Lightwave Logic Inc.
Inventor: Michael Lebby
Integrated epitaxial metal electrodes
Patent number: 10825912
Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer.
Type: Grant
Filed: November 1, 2018
Date of Patent: November 3, 2020
Assignee: IQE plc
Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
DIRECT DRIVE REGION-LESS POLYMER MODULATOR METHODS OF FABRICATING AND MATERIALS THEREFOR
Publication number: 20200285085
Abstract: A direct-drive region-less polymer modulator includes a waveguide having a first cladding layer, a passive core with a surface abutting the first cladding layer, the passive core extending to an optical input and an optical output. A shaped electro-optic polymer active component with a surface abutting the passive core region, the shaped component being polled to align dipoles and promote modulation of light and having a length that extends only within a modulation area defined by modulation electrodes. A second cladding layer enclosing the shaped component and designed to produce adiabatic transition of light waves traveling in the passive core region into the shaped component to travel the length of the shaped component and return to the passive core region. A portion of the multilayer waveguide defining the polymer modulator as a direct-drive polymer modulator.
Type: Application
Filed: February 11, 2020
Publication date: September 10, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami
Fabrication process of polymer based photonic apparatus and the apparatus
Patent number: 10754093
Abstract: A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.
Type: Grant
Filed: May 14, 2019
Date of Patent: August 25, 2020
Assignee: Lightwave Logic Inc.
Inventors: Zhiming Liu, Michael Lebby, Brian Shaw, Richard Becker, Youngwoo Yi
ACTIVE REGION-LESS POLYMER MODULATOR INTEGRATED ON A COMMON PIC PLATFORM AND METHOD
Publication number: 20200183201
Abstract: A monolithic PIC including a monolithic laser formed in/on a platform and a polymer modulator monolithically built onto the platform and optically coupled to the laser. The modulator includes a first cladding layer, a passive core region with a surface abutting a surface of the first cladding layer, the core region extending to define an input and an output for the modulator. A shaped electro-optic polymer active component has a surface abutting a surface of a central portion of the core region. The active component is polled to align dipoles and promote modulation of light and has a length that extends only within a modulation area defined by modulation electrodes. A second cladding layer encloses the active component and is designed to produce adiabatic transition of light waves traveling in the core region into the active component to travel the length thereof and return to the core region.
Type: Application
Filed: December 11, 2019
Publication date: June 11, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Yasufumi Enami
III-N TO RARE EARTH TRANSITION IN A SEMICONDUCTOR STRUCTURE
Publication number: 20200161417
Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
Type: Application
Filed: November 19, 2019
Publication date: May 21, 2020
Inventors: Rytis Dargis, Andrew Clark, Rodney Pelzel, Michael Lebby, Robert Yanka
CONDUCTIVE MULTI-FIBER/PORT HERMETIC CAPSULE AND METHOD
Publication number: 20200150363
Abstract: A conductive hermetically sealed monolithic photonic integrated circuit with optical components and multiple optical and electrical inputs/outputs includes a semiconductor/metal base having sensitive components with multiple optical and electrical inputs, multiple optical and electrical outputs, and/or multiple optical and electrical inputs and outputs. An electrically conductive basic lid includes at least two of metal, dielectric and semiconductor materials combined to form an electrically conductive protective circuit. The conductive basic lid is sealed to the semiconductor/metal base by metallization so as to form a chamber including the sensitive components and hermetically sealing the chamber and the sensitive component from the ambient in a basic hermetic capsule and the electrically conductive protective circuit is formed and connected to protect the sensitive components from external electrical interference.
Type: Application
Filed: November 9, 2018
Publication date: May 14, 2020
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
HERMETIC CAPSULE AND METHOD
Publication number: 20200119516
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Application
Filed: December 15, 2019
Publication date: April 16, 2020
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
Pnictide buffer structures and devices for GaN base applications
Patent number: 10615141
Abstract: A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
Type: Grant
Filed: June 2, 2017
Date of Patent: April 7, 2020
Assignee: IQE plc
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Re-based integrated photonic and electronic layered structures
Patent number: 10605987
Abstract: Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
Type: Grant
Filed: January 18, 2019
Date of Patent: March 31, 2020
Assignee: IQE plc
Inventors: Andrew Clark, Rich Hammond, Rytis Dargis, Michael Lebby, Rodney Pelzel
GUIDE TRANSITION DEVICE AND METHOD
Publication number: 20200088939
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 8, 2019
Publication date: March 19, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J. Leonberger, Richard Becker
PROTECTION LAYERS FOR POLYMER MODULATORS/WAVEGUIDES
Publication number: 20200088941
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Application
Filed: November 21, 2019
Publication date: March 19, 2020
Applicant: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Direct-drive polymer modulator methods of fabricating and materials therefor
Patent number: 10591755
Abstract: A direct-drive polymer modulator including a platform, a multilayer waveguide formed in/on the platform, the waveguide including a bottom cladding layer, an electro-optic polymer core and a top cladding layer, and at least a portion of the waveguide forming a direct-drive polymer modulator.
Type: Grant
Filed: February 19, 2018
Date of Patent: March 17, 2020
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Frederick J Leonberger, Michael Lebby
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20200083668
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 11, 2019
Publication date: March 12, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Epitaxial AIN/cREO structure for RF filter applications
Patent number: 10573686
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Grant
Filed: June 19, 2017
Date of Patent: February 25, 2020
Assignee: IQE plc
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Hermetic capsule and method for a monolithic photonic integrated circuit
Patent number: 10574025
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Grant
Filed: January 26, 2018
Date of Patent: February 25, 2020
Assignee: Lightwave Logic Inc.
Inventor: Michael Lebby
Layer structures for RF filters fabricated using rare earth oxides and epitaxial aluminum nitride
Patent number: 10566944
Abstract: Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure can include an epitaxial crystalline rare earth oxide (REO) layer over a substrate, a first epitaxial electrode layer over the crystalline REO layer, and an epitaxial piezoelectric layer over the first epitaxial electrode layer. The layer structure can further include a second electrode layer over the epitaxial piezoelectric layer. The first electrode layer can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
Type: Grant
Filed: September 10, 2018
Date of Patent: February 18, 2020
Assignee: IQE plc
Inventors: Rodney Pelzel, Rytis Dargis, Andrew Clark, Howard Williams, Patrick Chin, Michael Lebby
Polymer modulator and laser integrated on a common platform and method
Patent number: 10527786
Abstract: A monolithic photonic integrated circuit includes a platform, a monolithic laser formed in/on the platform, and an electro-optic polymer modulator monolithically built onto the platform and optically coupled to the monolithic laser. The polymer modulator is optically coupled to the monolithic laser by waveguides including electro-optic polymer waveguides. The electro-optic polymer modulator and the electro-optic polymer waveguides including an electro-optic polymer core and top and bottom electro-optic polymer cladding layers. The electro-optic polymer core having an electro-optic coefficient (r33) greater than 250 pm/v, and a Tg 150° C. to 200° C., and the top and bottom electro-optic polymer cladding layers having a Tg approximately the same as the Tg of the electro-optic polymer core.
Type: Grant
Filed: August 31, 2017
Date of Patent: January 7, 2020
Assignee: Lightwave Logic Inc.
Inventors: Frederick J Leonberger, Michael Lebby, Richard Becker
Protection layers for polymer modulators/waveguides
Patent number: 10520673
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Grant
Filed: December 28, 2017
Date of Patent: December 31, 2019
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Guide transition device and method
Patent number: 10509164
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: September 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger, Richard Becker
Guide transition device with digital grating deflectors and method
Patent number: 10511146
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: November 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
FABRICATION PROCESS OF POLYMER BASED PHOTONIC APPARATUS AND THE APPARTUS
Publication number: 20190353843
Abstract: A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.
Type: Application
Filed: May 14, 2019
Publication date: November 21, 2019
Applicant: Lightwave Logic Inc.
Inventors: Zhiming Liu, Michael Lebby, Brian Shaw, Richard Becker, Youngwoo Yi
EPITAXIAL AIN/cREO STRUCTURE FOR RF FILTER APPLICATIONS
Publication number: 20190305039
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Application
Filed: June 19, 2017
Publication date: October 3, 2019
Applicant: IQE plc.
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
EMBEDDED HERMETIC CAPSULE AND METHOD
Publication number: 20190278036
Abstract: An embedded hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal embedded lid. The semiconductor/metal embedded lid sealed to the semiconductor/metal base by metallization so as to form a chamber including at least one of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient in an embedded hermetic capsule. External access to the sensitive semiconductor/polymer electrical and optical components is provided through the metallization.
Type: Application
Filed: March 7, 2018
Publication date: September 12, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
HERMETIC CAPSULE AND METHOD
Publication number: 20190237930
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Application
Filed: January 26, 2018
Publication date: August 1, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
RE-based Integrated Photonic and Electronic Layered Structures
Publication number: 20190227233
Abstract: Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
Type: Application
Filed: January 18, 2019
Publication date: July 25, 2019
Inventors: Andrew Clark, Rich Hammond, Rytis Dargis, Michael Lebby, Rodney Pelzel
POROUS DISTRIBUTED BRAGG REFLECTORS FOR LASER APPLICATIONS
Publication number: 20190221993
Abstract: Embodiments described herein provide a layered structure that comprises a substrate that includes a first porous multilayer of a first porosity, an active quantum well capping layer epitaxially grown over the first porous multilayer, and a second porous multilayer of the first porosity over the active quantum well capping layer, where the second porous multilayer aligns with the first porous multilayer.
Type: Application
Filed: January 18, 2019
Publication date: July 18, 2019
Inventors: Rich Hammond, Rodney Pelzel, Drew Nelson, Andrew Clark, David Cheskis, Michael Lebby
PROTECTION LAYERS FOR POLYMER MODULATORS/WAVEGUIDES
Publication number: 20190204506
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Application
Filed: December 28, 2017
Publication date: July 4, 2019
Applicant: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Rare earth pnictides for strain management
Patent number: 10332857
Abstract: Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.
Type: Grant
Filed: June 2, 2017
Date of Patent: June 25, 2019
Assignee: IQE plc
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Integrated Epitaxial Metal Electrodes
Publication number: 20190172923
Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.
Type: Application
Filed: January 25, 2019
Publication date: June 6, 2019
Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20190148913
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 14, 2017
Publication date: May 16, 2019
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Pnictide Buffer Structures and Devices for GaN Base Applications
Publication number: 20190139761
Abstract: A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
Type: Application
Filed: June 2, 2017
Publication date: May 9, 2019
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
GROUP III SEMICONDUCTOR EPITAXY FORMED ON SILICON VIA SINGLE CRYSTAL REN AND REO BUFFER LAYERS
Publication number: 20190122885
Abstract: Layer structures are described for the formation of Group III-V semiconductor material over Si<110> and Si<100>. Various buffer layers and interfaces reduce the lattice strain between the Group III-V semiconductor material and the Si<110> or Si<100> layers, allowing for the epitaxial formation of high quality Group III-V semiconductor material.
Type: Application
Filed: April 10, 2017
Publication date: April 25, 2019
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby, Rodney Pelzel
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20200083668
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 11, 2019
Publication date: March 12, 2020
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Epitaxial AIN/cREO structure for RF filter applications
Patent number: 10573686
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Grant
Filed: June 19, 2017
Date of Patent: February 25, 2020
Assignee: IQE plc
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Hermetic capsule and method for a monolithic photonic integrated circuit
Patent number: 10574025
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Grant
Filed: January 26, 2018
Date of Patent: February 25, 2020
Assignee: Lightwave Logic Inc.
Inventor: Michael Lebby
Layer structures for RF filters fabricated using rare earth oxides and epitaxial aluminum nitride
Patent number: 10566944
Abstract: Layer structures for RF filters can be fabricated using rare earth oxides and epitaxial aluminum nitride, and methods for growing the layer structures. A layer structure can include an epitaxial crystalline rare earth oxide (REO) layer over a substrate, a first epitaxial electrode layer over the crystalline REO layer, and an epitaxial piezoelectric layer over the first epitaxial electrode layer. The layer structure can further include a second electrode layer over the epitaxial piezoelectric layer. The first electrode layer can include an epitaxial metal. The epitaxial metal can be single-crystal. The first electrode layer can include one or more of a rare earth pnictide, and a rare earth silicide (RESi).
Type: Grant
Filed: September 10, 2018
Date of Patent: February 18, 2020
Assignee: IQE plc
Inventors: Rodney Pelzel, Rytis Dargis, Andrew Clark, Howard Williams, Patrick Chin, Michael Lebby
Polymer modulator and laser integrated on a common platform and method
Patent number: 10527786
Abstract: A monolithic photonic integrated circuit includes a platform, a monolithic laser formed in/on the platform, and an electro-optic polymer modulator monolithically built onto the platform and optically coupled to the monolithic laser. The polymer modulator is optically coupled to the monolithic laser by waveguides including electro-optic polymer waveguides. The electro-optic polymer modulator and the electro-optic polymer waveguides including an electro-optic polymer core and top and bottom electro-optic polymer cladding layers. The electro-optic polymer core having an electro-optic coefficient (r33) greater than 250 pm/v, and a Tg 150° C. to 200° C., and the top and bottom electro-optic polymer cladding layers having a Tg approximately the same as the Tg of the electro-optic polymer core.
Type: Grant
Filed: August 31, 2017
Date of Patent: January 7, 2020
Assignee: Lightwave Logic Inc.
Inventors: Frederick J Leonberger, Michael Lebby, Richard Becker
Protection layers for polymer modulators/waveguides
Patent number: 10520673
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Grant
Filed: December 28, 2017
Date of Patent: December 31, 2019
Assignee: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Guide transition device and method
Patent number: 10509164
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: September 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger, Richard Becker
Guide transition device with digital grating deflectors and method
Patent number: 10511146
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Grant
Filed: November 14, 2017
Date of Patent: December 17, 2019
Assignee: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
FABRICATION PROCESS OF POLYMER BASED PHOTONIC APPARATUS AND THE APPARTUS
Publication number: 20190353843
Abstract: A method of fabricating polymer modulators includes forming an insulating layer on a platform and depositing and patterning a ground electrode on the insulating layer. A bottom polymer cladding layer, a first blocking layer, a polymer core layer, a second blocking layer, and a top polymer cladding layer are deposited in order. A third blocking layer is deposited on the top cladding layer and patterned to define vias which are used to etch ground openings through the top polymer cladding layer, the second blocking layer, the core layer, the first blocking layer, and the bottom cladding layer to the ground electrode. The openings are filled with electrically conductive material from electrical communication with the ground electrode to a surface of the top polymer cladding layer. The third blocking layer is removed and electrical contacts are formed on the top polymer cladding layer in electrical communication with the electrically conductive material.
Type: Application
Filed: May 14, 2019
Publication date: November 21, 2019
Applicant: Lightwave Logic Inc.
Inventors: Zhiming Liu, Michael Lebby, Brian Shaw, Richard Becker, Youngwoo Yi
EPITAXIAL AIN/cREO STRUCTURE FOR RF FILTER APPLICATIONS
Publication number: 20190305039
Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.
Type: Application
Filed: June 19, 2017
Publication date: October 3, 2019
Applicant: IQE plc.
Inventors: Wang Nang Wang, Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
EMBEDDED HERMETIC CAPSULE AND METHOD
Publication number: 20190278036
Abstract: An embedded hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal embedded lid. The semiconductor/metal embedded lid sealed to the semiconductor/metal base by metallization so as to form a chamber including at least one of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient in an embedded hermetic capsule. External access to the sensitive semiconductor/polymer electrical and optical components is provided through the metallization.
Type: Application
Filed: March 7, 2018
Publication date: September 12, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
HERMETIC CAPSULE AND METHOD
Publication number: 20190237930
Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.
Type: Application
Filed: January 26, 2018
Publication date: August 1, 2019
Applicant: Lightwave Logic Inc.
Inventor: Michael Lebby
RE-based Integrated Photonic and Electronic Layered Structures
Publication number: 20190227233
Abstract: Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.
Type: Application
Filed: January 18, 2019
Publication date: July 25, 2019
Inventors: Andrew Clark, Rich Hammond, Rytis Dargis, Michael Lebby, Rodney Pelzel
POROUS DISTRIBUTED BRAGG REFLECTORS FOR LASER APPLICATIONS
Publication number: 20190221993
Abstract: Embodiments described herein provide a layered structure that comprises a substrate that includes a first porous multilayer of a first porosity, an active quantum well capping layer epitaxially grown over the first porous multilayer, and a second porous multilayer of the first porosity over the active quantum well capping layer, where the second porous multilayer aligns with the first porous multilayer.
Type: Application
Filed: January 18, 2019
Publication date: July 18, 2019
Inventors: Rich Hammond, Rodney Pelzel, Drew Nelson, Andrew Clark, David Cheskis, Michael Lebby
PROTECTION LAYERS FOR POLYMER MODULATORS/WAVEGUIDES
Publication number: 20190204506
Abstract: A polymer waveguide/modulator including a lower cladding layer, a polymer core, an upper cladding layer, a first protection/barrier layer sandwiched between the lower cladding layer and the core, and a second protection/barrier layer sandwiched between the core and the upper cladding layer. The protection/barrier layers designed to protect the cladding layers and the core from solvents and gases and to prevent current leakage between the cladding layers and the core. The first protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the lower cladding layer. The second protection/barrier layer is optically transparent and designed with a refractive index less than, greater than, or the same as the refractive index of the core and approximately equal to the refractive index of the upper cladding layer.
Type: Application
Filed: December 28, 2017
Publication date: July 4, 2019
Applicant: Lightwave Logic Inc.
Inventors: Richard Becker, Michael Lebby, Youngwoo Yi
Rare earth pnictides for strain management
Patent number: 10332857
Abstract: Systems and methods described herein may include a first semiconductor layer with a first lattice constant, a rare earth pnictide buffer epitaxially grown over the first semiconductor, wherein a first region of the rare earth pnictide buffer adjacent to the first semiconductor has a net strain that is less than 1%, a second semiconductor layer epitaxially grown over the rare earth pnictide buffer, wherein a second region of the rare earth pnictide buffer adjacent to the second semiconductor has a net strain that is a desired strain, and wherein the rare earth pnictide buffer may comprise one or more rare earth elements and one or more Group V elements. In some examples, the desired strain is approximately zero.
Type: Grant
Filed: June 2, 2017
Date of Patent: June 25, 2019
Assignee: IQE plc
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
Integrated Epitaxial Metal Electrodes
Publication number: 20190172923
Abstract: Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.
Type: Application
Filed: January 25, 2019
Publication date: June 6, 2019
Inventors: Rodney Pelzel, Andrew Clark, Rytis Dargis, Patrick Chin, Michael Lebby
GUIDE TRANSITION DEVICE WITH DIGITAL GRATING DEFLECTORS AND METHOD
Publication number: 20190148913
Abstract: A guide transition device including a light source designed to generate a light beam, a light input port on a first plane and coupled to receive the light beam from the light source, a light output port on a second plane different than the first plane, the light output port designed to couple a received light beam to output equipment and plane shifting apparatus coupled to receive the light beam from the light input port on the first plane and to shift or transfer the light beam to the second plane. The plane shifting apparatus including one or more digital gratings each designed to deflect the light beam approximately ninety degrees. The plane shifting apparatus is coupled to transfer the light beam to the light output port on the second plane.
Type: Application
Filed: November 14, 2017
Publication date: May 16, 2019
Applicant: Lightwave Logic Inc.
Inventors: Michael Lebby, Frederick J Leonberger
Pnictide Buffer Structures and Devices for GaN Base Applications
Publication number: 20190139761
Abstract: A structure can include a III-N layer with a first lattice constant, a first rare earth pnictide layer with a second lattice constant epitaxially grown over the III-N layer, a second rare earth pnictide layer with a third lattice constant epitaxially grown over the first rare earth pnictide layer, and a semiconductor layer with a fourth lattice constant epitaxially grown over the second rare earth pnictide layer. A first difference between the first lattice constant and the second lattice constant and a second difference between the third lattice constant and the fourth lattice constant are less than one percent.
Type: Application
Filed: June 2, 2017
Publication date: May 9, 2019
Inventors: Andrew Clark, Rytis Dargis, Michael Lebby, Rodney Pelzel
GROUP III SEMICONDUCTOR EPITAXY FORMED ON SILICON VIA SINGLE CRYSTAL REN AND REO BUFFER LAYERS
Publication number: 20190122885
Abstract: Layer structures are described for the formation of Group III-V semiconductor material over Si<110> and Si<100>. Various buffer layers and interfaces reduce the lattice strain between the Group III-V semiconductor material and the Si<110> or Si<100> layers, allowing for the epitaxial formation of high quality Group III-V semiconductor material.
Type: Application
Filed: April 10, 2017
Publication date: April 25, 2019
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby, Rodney Pelzel
REO gate dielectric for III-N device on Si substrate
Patent number: 8878188
Abstract: A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material.
Type: Grant
Filed: February 22, 2013
Date of Patent: November 4, 2014
Assignee: Translucent, Inc.
Inventors: Rytis Dargis, Robin Smith, Andrew Clark, Erdem Arkun, Michael Lebby
AlN cap grown on GaN/REO/silicon substrate structure
Patent number: 8872308
Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
Type: Grant
Filed: February 20, 2013
Date of Patent: October 28, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
IIIONon single crystal SOI substrate and III n growth platform
Patent number: 8835955
Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
Type: Grant
Filed: August 30, 2011
Date of Patent: September 16, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Rytis Dargis, Andrew Clark, Michael Lebby
REO/ALO/A1N template for III-N material growth on silicon
Patent number: 8823055
Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.
Type: Grant
Filed: December 17, 2012
Date of Patent: September 2, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
III-N material grown on AIO/AIN buffer on Si substrate
Patent number: 8823025
Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Grant
Filed: February 20, 2013
Date of Patent: September 2, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE
Publication number: 20140239307
Abstract: A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material.
Type: Application
Filed: February 22, 2013
Publication date: August 28, 2014
Inventors: RYTIS DARGIS, ROBIN SMITH, ANDREW CLARK, ERDEM ARKUN, MICHAEL LEBBY
AlN CAP GROWN ON GaN/REO/SILICON SUBSTRATE STRUCTURE
Publication number: 20140231818
Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
Type: Application
Filed: February 20, 2013
Publication date: August 21, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
III-N MATERIAL GROWN ON ALO/ALN BUFFER ON SI SUBSTRATE
Publication number: 20140231817
Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Application
Filed: February 20, 2013
Publication date: August 21, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON
Publication number: 20140225123
Abstract: A III-N template formed on a silicon substrate includes a Distributed Bragg Reflector positioned on the silicon substrate. The Distributed Bragg Reflector is substantially crystal lattice matched to the surface of the silicon substrate. An aluminum oxide layer is positioned on the surface of the Distributed Bragg Reflector and substantially crystal lattice matched to the surface of the Distributed Bragg Reflector. A layer of aluminum nitride (AlN) is positioned on the surface of the aluminum oxide layer and substantially crystal lattice matched to the surface of the aluminum oxide layer. A III-N LED structure including at least one III-N layer can then be grown on the aluminum nitride layer and substantially crystal lattice matched to the surface of the aluminum nitride layer.
Type: Application
Filed: February 13, 2014
Publication date: August 14, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
Laser cooling of modified SOI wafer
Patent number: 8794010
Abstract: A laser cooling system includes a substrate, an REO layer of single crystal rare earth oxide including at least one rare earth element positioned on the surface of the substrate, and an active layer of single crystal semiconductor material positioned on the REO layer to form a semiconductor-on-insulator (SOI) device. Light guiding structure is at least partially formed by the REO layer so as to introduce energy elements into the REO layer and produce cooling by anti-Stokes fluorescence. The active layer of single crystal semiconductor material is positioned on the REO layer in proximity to the light guiding structure so as to receive the cooling.
Type: Grant
Filed: December 13, 2010
Date of Patent: August 5, 2014
Assignee: Translucent, Inc.
Inventors: David L. Williams, Andrew Clark, Michael Lebby
REO/ALO/AlN TEMPLATE FOR III-N MATERIAL GROWTH ON SILICON
Publication number: 20140167057
Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.
Type: Application
Filed: December 17, 2012
Publication date: June 19, 2014
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
Re-silicide gate electrode for III-N device on Si substrate
Patent number: 8748900
Abstract: A method of fabricating a rare earth silicide gate electrode on III-N material grown on a silicon substrate includes growing a single crystal stress compensating template on a silicon substrate. The template is substantially crystal lattice matched to the surface of the silicon substrate. A single crystal GaN structure is grown on the surface of the template and substantially crystal lattice matched to the template. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched to the GaN structure. A single crystal monoclinic rare earth oxide dielectric layer is grown on the active layer of III-N material and a single crystal rare earth silicide gate electrode is grown on the dielectric layer, the silicide. Relative portions of the gadolinium metal and the silicon are adjusted during deposition so they react to form rare earth silicide during deposition.
Type: Grant
Filed: March 27, 2013
Date of Patent: June 10, 2014
Assignee: Translucent, Inc.
Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun, Robin Smith, Michael Lebby
A1N inter-layers in III-N material grown on DBR/silicon substrate
Patent number: 8680507
Abstract: A DBR/gallium nitride/aluminum nitride base grown on a silicon substrate includes a Distributed Bragg Reflector (DBR) positioned on the silicon substrate. The DBR is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the DBR, an inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Grant
Filed: January 16, 2013
Date of Patent: March 25, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
DELTA DOPING AT Si-Ge INTERFACE
Publication number: 20140077339
Abstract: A IV or III-V device is fabricated on a germanium template on a silicon substrate and includes a thin layer of Ge epitaxially grown on a silicon substrate. The thin layer includes Ge delta doped with Sn at the silicon substrate. A single crystal layer of Ge is epitaxially grown on the thin layer of Ge doped with Sn. A structure including one of IV material and III-V material is epitaxially grown on the single crystal layer of Ge.
Type: Application
Filed: September 14, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
Si-Ge-Sn ON REO TEMPLATE
Publication number: 20140077338
Abstract: An electronic device includes IV material grown on a silicon substrate. The device includes a crystalline silicon substrate and a rare earth structure epitaxially grown on the silicon substrate. The rare earth structure includes a layer of a rare earth oxide with electrical insulating characteristics so that the rare earth structure provides electrical insulation from the silicon substrate. A single crystal IV material film is epitaxially grown on the rare earth structure. The single crystal IV material film includes one of crystal lattice matching or crystal lattice mismatching the IV material film to the rare earth structure.
Type: Application
Filed: September 14, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
IV MATERIAL PHOTONIC DEVICE ON DBR
Publication number: 20140077240
Abstract: A photonic structure including a substrate of either crystalline silicon or germanium and a multilayer distributed Bragg reflector (DBR) positioned on the substrate. The DBR includes material substantially crystal lattice matching the DBR to the substrate. The DBR includes a plurality of pairs of layers of material including any combination of IV materials and any rare earth oxide (REO). A photonic device including multilayers of single crystal IV material positioned on the DBR and including material substantially crystal lattice matching the DBR to the photonic device.
Type: Application
Filed: September 17, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans, Andrew Clark
III-V SEMICONDUCTOR INTERFACE WITH GRADED GeSn ON SILICON
Publication number: 20140076390
Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.
Type: Application
Filed: September 14, 2012
Publication date: March 20, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
GRADED GeSn ON SILICON
Publication number: 20140053894
Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 ?m to approximately 5 ?m. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.
Type: Application
Filed: August 23, 2012
Publication date: February 27, 2014
Inventors: Radek Roucka, Michael Lebby, Scott Semans
Solar cells with engineered spectral conversion
Patent number: 8637763
Abstract: A solar cell with engineered spectral conversion elements or components includes a single crystal silicon solar cell having a back surface. At least one spectral conversion element is formed on the back surface. The conversion element includes single crystal rare earth oxide, and the single crystal rare earth oxide is crystal lattice matched to the back surface of the silicon solar cell. Material including silicon is formed on the back surface in a surrounding and embedding relationship to the at least one spectral conversion element. A back reflector is positioned on the material formed on the back surface so as to reflect light passing through the silicon formed on the back surface.
Type: Grant
Filed: May 26, 2010
Date of Patent: January 28, 2014
Assignee: Translucent, Inc.
Inventors: Michael Lebby, Andrew Clark
Oxygen engineered single-crystal REO template
Patent number: 8636844
Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
Type: Grant
Filed: July 6, 2012
Date of Patent: January 28, 2014
Assignee: Translucent, Inc.
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
AlN inter-layers in III-N material grown on REO/silicon substrate
Patent number: 8633569
Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
Type: Grant
Filed: January 16, 2013
Date of Patent: January 21, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
OXYGEN ENGINEERED SINGLE-CRYSTAL REO TEMPLATE
Publication number: 20140008644
Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
Type: Application
Filed: July 6, 2012
Publication date: January 9, 2014
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
Silicon, aluminum oxide, aluminum nitride template for optoelectronic and power devices
Patent number: 8623747
Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes forming an aluminum oxide coating on the surface of the silicon substrate, the aluminum oxide being substantially crystal lattice matched to the surface of the silicon substrate and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide coating substantially crystal lattice matched to the surface of the aluminum nitride.
Type: Grant
Filed: December 17, 2012
Date of Patent: January 7, 2014
Assignee: Translucent, Inc.
Inventors: Erdem Arkun, Michael Lebby, Andrew Clark
SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx
Publication number: 20130334536
Abstract: A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide.
Type: Application
Filed: February 20, 2013
Publication date: December 19, 2013
Inventors: Rytis Dargis, Andrew Clark, Robin Smith, Michael Lebby
Integrated pump laser and rare earth waveguide amplifier
Patent number: 8559097
Abstract: A light amplifier includes a single crystal semiconductor substrate with a rare earth oxide, light amplifying gain medium deposited on the substrate and formed into a light waveguide, and a pump laser. A lattice matching virtual substrate integrates the pump laser to the gain medium with a first opposed surface crystal lattice matched to the gain medium and second opposed surface crystal lattice matched to the pump laser. The pump laser is positioned with a light output surface coupled to a light input surface of the gain medium so as to introduce pump energy into the light waveguide. The light amplifier has a very small footprint and allows the integration of control and monitoring electronics.
Type: Grant
Filed: July 21, 2010
Date of Patent: October 15, 2013
Assignee: Translucent, Inc.
Inventors: David L. Williams, Andrew Clark, Michael Lebby
Integrated rare earth devices
Patent number: 8553741
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Grant
Filed: November 12, 2012
Date of Patent: October 8, 2013
Assignee: Translucent Inc.
Inventor: Michael Lebby
NUCLEATION OF III-N ON REO TEMPLATES
Publication number: 20130248853
Abstract: A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon.
Type: Application
Filed: March 18, 2013
Publication date: September 26, 2013
Inventors: Erdem Arkun, Andrew Clark, Rytis Dargis, Radek Roucka, Michael Lebby
III-N ON SILICON USING NANO STRUCTURED INTERFACE LAYER
Publication number: 20130214282
Abstract: A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent.
Type: Application
Filed: February 17, 2012
Publication date: August 22, 2013
Inventors: Erdem Arkun, Radek Roucka, Andrew Clark, Robin Smith, Michael Lebby
Modification of REO by subsequent III-N EPI process
Patent number: 8501635
Abstract: A method of growing single crystal III-N material on a semiconductor substrate includes providing a substrate including one of crystalline silicon or germanium and a layer of rare earth oxide. A layer of single crystal III-N material is epitaxially grown on the substrate using a process that elevates the temperature of the layer of rare earth oxide into a range of approximately 750° C. to approximately 1250° C. in the presence of an N or a III containing species, whereby a portion of the layer of rare earth oxide is transformed to a new alloy.
Type: Grant
Filed: September 29, 2012
Date of Patent: August 6, 2013
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Rytis Dargis, Erdem Arkun, Michael Lebby
REO-Si TEMPLATE WITH INTEGRATED REO LAYERS FOR LIGHT EMISSION
Publication number: 20130153918
Abstract: A III-N on silicon LED constructed to emit light in the visible range includes a layer of single crystal III-N with a light emitting diode formed therein and designed to emit light at a first wavelength through a lower surface, a REO-Si template mated to the layer of single crystal III-N and designed to approximately crystal lattice match a silicon substrate, and a light emission layer of rare earth oxide selected to receive and absorb light at the first wavelength, up-convert the absorbed light, and re-emit light at a second wavelength in the visible range. The lower surface of the REO-Si template is either mated to the upper surface of a crystalline silicon substrate with the light emission layer integrated into the REO-Si template or mated to an upper surface of the light emission layer with a lower surface of the light emission layer mated to the crystalline silicon substrate.
Type: Application
Filed: December 16, 2011
Publication date: June 20, 2013
Inventors: Andrew Clark, Michael Lebby
High efficiency solar cell using IIIB material transition layers
Patent number: 8455756
Abstract: A solar cell including a base of single crystal silicon with a cubic crystal structure and a single crystal layer of a second material with a higher bandgap than the bandgap of silicon. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the base and the layer of second material with the one surface lattice matched to the base and the opposed surface lattice matched to the layer of second material.
Type: Grant
Filed: February 19, 2010
Date of Patent: June 4, 2013
Assignee: Translucent, Inc.
Inventors: Michael Lebby, Andrew Clark
STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON
Publication number: 20130099357
Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
Type: Application
Filed: October 21, 2011
Publication date: April 25, 2013
Inventors: Rytis Dargis, Erdem Arkun, Radek Roucka, Andrew Clark, Michael Lebby
INTEGRATED RARE EARTH DEVICES
Publication number: 20130071960
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Application
Filed: November 12, 2012
Publication date: March 21, 2013
Inventor: MICHAEL LEBBY
LATTICE MATCHED CRYSTALLINE REFLECTOR
Publication number: 20130062610
Abstract: A virtual substrate structure with a lattice matched crystalline reflector for a light emitting device including a single crystal rare earth oxide layer deposited on a silicon substrate and substantially crystal lattice matched to the silicon substrate. A reflective layer of single crystal electrically conductive material is deposited on the layer of single crystal rare earth oxide and a layer of single crystal semiconductor material is positioned in overlying relationship to the reflective layer and substantially crystal lattice matched to the reflective layer. A single crystal rare earth oxide layer is optionally deposited between the reflective layer and the layer of semiconductor material.
Type: Application
Filed: September 14, 2011
Publication date: March 14, 2013
Inventors: Andrew Clark, Michael Lebby, Robin Smith, David Williams
III-N FET ON SILICON USING FIELD SUPPRESSING REO
Publication number: 20130062609
Abstract: A III-N on silicon substrate with enhanced breakdown voltage including a rare earth oxide structure deposited on the silicon substrate and a layer of single crystal III-N semiconductor material deposited on the rare earth oxide structure. The rare earth oxide has a dielectric constant greater (approximately twice) than the III-N semiconductor material. The rare earth oxide structure is selected to cooperate with the layer of single crystal III-N semiconductor material to reduce the thickness of the layer of single crystal III-N semiconductor material required for a selected breakdown voltage to a value less than a thickness of the layer of single crystal III-N semiconductor material for the selected breakdown voltage without the cooperating single crystal rare earth oxide.
Type: Application
Filed: September 14, 2011
Publication date: March 14, 2013
Inventors: Robin Smith, David Williams, Rytis Dargis, Michael Lebby
Single crystal reo buffer on amorphous SiO
Patent number: 8394194
Abstract: A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide.
Type: Grant
Filed: June 13, 2012
Date of Patent: March 12, 2013
Inventors: Rytis Dargis, Andrew Clark, Robin Smith, Michael Lebby
RARE EARTH OXY-NITRIDE BUFFERED III-N ON SILICON
Publication number: 20130032858
Abstract: Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer of single crystal rare earth oxy-nitride is deposited on the REO structure. The REO structure is stress engineered to approximately crystal lattice match the layer of rare earth oxy-nitride so as to provide a predetermined amount of stress in the layer of rare earth oxy-nitride. A III oxy-nitride structure, including several layers of single crystal rare earth oxy-nitride, is deposited on the layer of rare earth oxy-nitride. A layer of single crystal III-N nitride is deposited on the III oxy-nitride structure. The III oxy-nitride structure is chemically engineered to approximately crystal lattice match the layer of III-N nitride and to transfer the predetermined amount of stress in the layer of rare earth oxy-nitride to the layer of III-N nitride.
Type: Application
Filed: August 3, 2011
Publication date: February 7, 2013
Inventors: Andrew Clark, Erdem Arkun, Robin Smith, Michael Lebby
Spontaneous/stimulated light emitting ?-cavity device
Patent number: 8331410
Abstract: A light emitting device with a ?-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-? erbium dielectric provides a high gain ?-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation.
Type: Grant
Filed: December 10, 2009
Date of Patent: December 11, 2012
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Integrated rare earth devices
Patent number: 8331413
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Grant
Filed: February 4, 2010
Date of Patent: December 11, 2012
Inventor: Michael Lebby
Single Crystal Ge On Si
Publication number: 20120280276
Abstract: A single crystal germanium-on-silicon structure includes a single crystal silicon substrate. A single crystal layer of gadolinium oxide is epitaxially grown on the substrate. The gadolinium oxide has a cubic crystal structure and a lattice spacing approximately equal to the lattice spacing or a multiple of the single crystal silicon. A single crystal layer of lanthanum oxide is epitaxially grown on the gadolinium oxide with a thickness of approximately 12 nm or less. The lanthanum oxide has a lattice spacing approximately equal to the lattice spacing or a multiple of single crystal germanium and a cubic crystal structure approximately similar to the cubic crystal structure of the gadolinium oxide. A single crystal layer of germanium with a (111) crystal orientation is epitaxially grown on the layer of lanthanum oxide.
Type: Application
Filed: March 20, 2012
Publication date: November 8, 2012
Inventors: Rytis Dargis, Erdem Arkun, Andrew Clark, Michael Lebby
Multilayer Rare Earth Device
Publication number: 20120256232
Abstract: Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed.
Type: Application
Filed: September 30, 2011
Publication date: October 11, 2012
Applicant: Translucent, Inc.
Inventors: Andrew Clark, F. Erdem Arkun, Michael Lebby
HEXAGONAL REO TEMPLATE BUFFER FOR III-N LAYERS ON SILICON
Publication number: 20120183767
Abstract: A III-N on silicon structure including a substrate of single crystal silicon with a cubic crystal structure and a layer of single crystal III-N material. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the substrate and the layer of III-N material with the one surface lattice matched to the substrate and the opposed surface lattice matched to the layer of III-N material.
Type: Application
Filed: December 16, 2011
Publication date: July 19, 2012
Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
LASER COOLING OF MODIFIED SOI WAFER
Publication number: 20120147906
Abstract: A laser cooling system includes a substrate, an REO layer of single crystal rare earth oxide including at least one rare earth element positioned on the surface of the substrate, and an active layer of single crystal semiconductor material positioned on the REO layer to form a semiconductor-on-insulator (SOI) device. Light guiding structure is at least partially formed by the REO layer so as to introduce energy elements into the REO layer and produce cooling by anti-Stokes fluorescence. The active layer of single crystal semiconductor material is positioned on the REO layer in proximity to the light guiding structure so as to receive the cooling.
Type: Application
Filed: December 13, 2010
Publication date: June 14, 2012
Inventors: David L. Williams, Andrew Clark, Michael Lebby
SOLAR CELLS WITH MAGNETICALLY ENHANCED UP-CONVERSION
Publication number: 20120145243
Abstract: A method of magnetically enhancing up-conversion components includes providing at least one of up-conversion material and sensitizer material (i.e. up-conversion components), generally in conjunction with a semiconductor solar cell, and positioning magnetic apparatus adjacent the up-conversion components to supply a magnetic field to the up-conversion components. The magnetic field has an intensity and direction selected to enhance operation of the up-conversion components.
Type: Application
Filed: December 10, 2010
Publication date: June 14, 2012
Inventors: David L. Williams, Andrew Clark, Michael Lebby
IIIOxNy ON REO/Si
Publication number: 20120104567
Abstract: An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A layer of single crystal IIIOxNy is formed in overlying relationship on the rare earth oxide by transitioning from the layer of rare earth oxide to a single crystal layer of IIIOxNy within a one wafer single epitaxial process. In the preferred embodiment the substrate is silicon, the rare earth oxide is Gd2O3, and the IIIOxNy includes AlOxNy.
Type: Application
Filed: August 12, 2011
Publication date: May 3, 2012
Inventors: Andrew Clark, Erdem Arkun, Michael Lebby
IIIOxNy ON SINGLE CRYSTAL SOI SUBSTRATE AND III n GROWTH PLATFORM
Publication number: 20120104443
Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
Type: Application
Filed: August 30, 2011
Publication date: May 3, 2012
Inventors: Andrew Clark, Michael Lebby, Erdem Arkun, Rytis Dargis
Photovoltaic conversion using rare earths plus Group IV Sensitizers
Publication number: 20120073648
Abstract: The invention relates to photovoltaic device structures of more than one layer comprising rare earth compounds and Group IV materials enabling spectral harvesting outside the conventional absorption limits for silicon.
Type: Application
Filed: September 24, 2010
Publication date: March 29, 2012
Inventors: Andrew Clark, Robin Smith, Scott Semans, F. Erdem Arkun, Michael Lebby
INTERGRATED PUMP LASER AND RARE EARTH WAVEGUIDE AMPLIFIER
Publication number: 20120019902
Abstract: A light amplifier includes a single crystal semiconductor substrate with a rare earth oxide, light amplifying gain medium deposited on the substrate and formed into a light waveguide, and a pump laser. A lattice matching virtual substrate integrates the pump laser to the gain medium with a first opposed surface crystal lattice matched to the gain medium and second opposed surface crystal lattice matched to the pump laser. The pump laser is positioned with a light output surface coupled to a light input surface of the gain medium so as to introduce pump energy into the light waveguide. The light amplifier has a very small footprint and allows the integration of control and monitoring electronics.
Type: Application
Filed: July 21, 2010
Publication date: January 26, 2012
Inventors: David L. Williams, Andrew Clark, Michael Lebby
SOLAR CELLS WITH ENGINEERED SPECTRAL CONVERSION
Publication number: 20110290313
Abstract: A solar cell with engineered spectral conversion elements or components includes a single crystal silicon solar cell having a back surface. At least one spectral conversion element is formed on the back surface. The conversion element includes single crystal rare earth oxide, and the single crystal rare earth oxide is crystal lattice matched to the back surface of the silicon solar cell. Material including silicon is formed on the back surface in a surrounding and embedding relationship to the at least one spectral conversion element. A back reflector is positioned on the material formed on the back surface so as to reflect light passing through the silicon formed on the back surface.
Type: Application
Filed: May 26, 2010
Publication date: December 1, 2011
Inventors: MICHAEL LEBBY, Andrew Clark
Multijunction rare earth solar cell
Patent number: 8049100
Abstract: Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed.
Type: Grant
Filed: November 16, 2009
Date of Patent: November 1, 2011
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Active rare earth tandem solar cell
Patent number: 8039738
Abstract: The use of rare-earth (RE and O, N, P) based materials to transition between two different semiconductor materials and enable up and/or down conversion of incident radiation is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacing enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds.
Type: Grant
Filed: November 16, 2009
Date of Patent: October 18, 2011
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Passive rare earth tandem solar cell
Patent number: 8039737
Abstract: The use of rare-earth (RE+O, N, P) based materials to transition between two semiconductor materials is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacings enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds. Disclosed embodiments include tandem solar cells.
Type: Grant
Filed: November 16, 2009
Date of Patent: October 18, 2011
Assignee: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
ACTIVE SOLAR CONCENTRATOR WITH MULTI-JUNCTION DEVICES
Publication number: 20110220173
Abstract: An active solar concentrator including a horizontally oriented structure including light directing portions with partially reflective surfaces directing light vertically impinging thereon into a central area and a solar module positioned in the central area to receive light from the partially reflective surfaces. The light directing portions each including at least one layer of rare earth oxide designed to up-convert light passing therethrough and positioned to receive light directly and/or from an outer light directing portion. The solar module may include a plurality of multi junction solar cells formed on a common substrate.
Type: Application
Filed: March 9, 2010
Publication date: September 15, 2011
Inventor: MICHAEL LEBBY
HIGH EFFICIENCY SOLAR CELL USING IIIB MATERIAL TRANSITION LAYERS
Publication number: 20110203666
Abstract: A solar cell including a base of single crystal silicon with a cubic crystal structure and a single crystal layer of a second material with a higher bandgap than the bandgap of silicon. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the base and the layer of second material with the one surface lattice matched to the base and the opposed surface lattice matched to the layer of second material.
Type: Application
Filed: February 19, 2010
Publication date: August 25, 2011
Inventors: Michael Lebby, Andrew Clark
INTEGRATED RARE EARTH DEVICES
Publication number: 20110188533
Abstract: The invention includes a single chip having multiple different devices integrated thereon for a common purpose. The chip includes a substrate having a peripheral area, a mid-chip area, and a central area. A plurality of FETs are formed in the peripheral area with each FET having a layer of single crystal rare earth material in at least one of a conductive channel, a gate insulator, or a gate stack. A plurality of photonic devices including light emitting diodes or vertical cavity surface emitting lasers are formed in the mid-chip area with each photonic device having an active layer of single crystal rare earth material. A plurality of photo detectors are formed in the central area.
Type: Application
Filed: February 4, 2010
Publication date: August 4, 2011
Inventor: MICHAEL LEBBY
Stacked transistors and process
Patent number: 7968384
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Grant
Filed: July 31, 2009
Date of Patent: June 28, 2011
Inventors: Petar B. Atanakovic, Michael Lebby
Full color display
Patent number: 7967653
Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Grant
Filed: September 28, 2009
Date of Patent: June 28, 2011
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
MULTILAYERED BOX IN FDSOI MOSFETS
Publication number: 20110108908
Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
Type: Application
Filed: September 29, 2010
Publication date: May 12, 2011
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Multilayered BOX in FDSOI MOSFETS
Patent number: 7821066
Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
Type: Grant
Filed: December 8, 2006
Date of Patent: October 26, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Passive Rare Earth Tandem Solar Cell
Publication number: 20100122720
Abstract: The use of rare-earth (RE+O, N, P) based materials to transition between two semiconductor materials is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacings enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds. Disclosed embodiments include tandem solar cells.
Type: Application
Filed: November 16, 2009
Publication date: May 20, 2010
Applicant: Translucent, Inc.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Active rare earth tandem solar cell
Publication number: 20100116315
Abstract: The use of rare-earth (RE and O, N, P) based materials to transition between two different semiconductor materials and enable up and/or down conversion of incident radiation is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacing enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds.
Type: Application
Filed: November 16, 2009
Publication date: May 13, 2010
Applicant: TRANSLUCENT, INC.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
Multijunction rare earth solar cell
Publication number: 20100109047
Abstract: Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed.
Type: Application
Filed: November 16, 2009
Publication date: May 6, 2010
Applicant: TRANSLUCENT, INC.
Inventors: Andrew Clark, Robin Smith, Richard Sewell, Scott Semans, F. Erdem Arkun, Michael Lebby
FULL COLOR DISPLAY
Publication number: 20100112736
Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Application
Filed: September 28, 2009
Publication date: May 6, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
SPONTANEOUS/STIMULATED LIGHT EMITTING ?-CAVITY DEVICE
Publication number: 20100084680
Abstract: A light emitting device with a p-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-? erbium dielectric provides a high gain ?-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation.
Type: Application
Filed: December 10, 2009
Publication date: April 8, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Spontaneous/stimulated light emitting ?-cavity device
Patent number: 7643526
Abstract: A light emitting device with a ?-cavity including a first spacer of single crystal dielectric material and an active area including single crystal erbium dielectric material positioned on the first spacer. The erbium dielectric material and the single crystal dielectric material of the first spacer are substantially crystal lattice matched at their juncture. A second spacer of single crystal dielectric material is positioned on the active area. The erbium dielectric material and the single crystal dielectric material of the second spacer are substantially crystal lattice matched at the second surface. The high-? erbium dielectric provides a high gain ?-cavity that emits increased amounts of light in either spontaneous or stimulated modes of operation.
Type: Grant
Filed: June 21, 2006
Date of Patent: January 5, 2010
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
STACKED TRANSISTORS AND PROCESS
Publication number: 20090291535
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Application
Filed: July 31, 2009
Publication date: November 26, 2009
Inventors: Petar B. Atanackovic, Michael Lebby
Full color display including LEDs with rare earth active areas and different radiative transistions
Patent number: 7605531
Abstract: A full color display comprising a red, a green, and a blue light emitting diode, each light emitting diode including a light emitting region having at least one layer of single crystal rare earth material, the rare earth material in each of the light emitting diodes having at least one radiative transition, and the rare earth material producing a radiation wavelength of approximately 640 nm in the red light emitting diode, 540 nm in the green light emitting diode, and 460 nm in the blue light emitting diode. Generally, the color of each LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Grant
Filed: October 25, 2005
Date of Patent: October 20, 2009
Assignee: Translucent, Inc.
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Stacked transistors and process
Patent number: 7579623
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Grant
Filed: July 22, 2005
Date of Patent: August 25, 2009
Assignee: Translucent, Inc.
Inventors: Petar B. Atanackovic, Michael Lebby
Signal and/or ground planes with double buried insulator layers and fabrication process
Patent number: 7538016
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Grant
Filed: December 20, 2007
Date of Patent: May 26, 2009
Assignee: Translucent, Inc.
Inventors: Petar B. Atanakovic, Michael Lebby
Selective colored light emitting diode
Patent number: 7388230
Abstract: A selective colored LED includes a light emitting area epitaxially grown on a first cladding layer, and a second cladding layer epitaxially grown on the light emitting area. The light emitting area includes at least one thin single crystal layer of rare earth material having at least one radiative transition producing a radiation wavelength of a selected color. The first cladding layer is positioned on a first mirror stack, with pairs of mirrors having an effective thickness of at least one half wavelength of the selected color, and a second mirror stack is positioned on the second cladding layer. Generally, the color of the LED is determined by selecting a rare earth with a radiative transition producing a radiation wavelength at the selected color. In cases where the rare earth has more than one radiative transition, tuned mirrors can be used to select the desired color.
Type: Grant
Filed: October 26, 2005
Date of Patent: June 17, 2008
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Multilayered box in FDSOI MOSFETS
Publication number: 20080135924
Abstract: A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.
Type: Application
Filed: December 8, 2006
Publication date: June 12, 2008
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Strain inducing multi-layer cap
Patent number: 7365357
Abstract: A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.
Type: Grant
Filed: July 22, 2005
Date of Patent: April 29, 2008
Assignee: Translucent Inc.
Inventors: Petar B. Atanackovic, Michael Lebby
SIGNAL AND/OR GROUND PLANES WITH DOUBLE BURIED INSULATOR LAYERS AND FABRICATION PROCESS
Publication number: 20080093670
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Application
Filed: December 20, 2007
Publication date: April 24, 2008
Applicant: TRANSLUCENT INC.
Inventors: Petar Atanakovic, MICHAEL LEBBY
IC on non-semiconductor substrate
Patent number: 7355269
Abstract: An integrated circuit and method of fabrication including a non-semiconductor material substrate with a layer of single crystal rare earth deposited on the surface thereof. A layer of single crystal semiconductor material is grown on the layer of single crystal rare earth and an integrated circuit is formed in the layer of single crystal semiconductor material. In a preferred embodiment the single crystal semiconductor material is silicon and the integrated circuit is formed by standard semiconductor industry processes.
Type: Grant
Filed: April 6, 2006
Date of Patent: April 8, 2008
Inventors: Michael Lebby, Vijit Sabnis, Petar B. Atanackovic
Signal and/or ground planes with double buried insulator layers and fabrication process
Patent number: 7323396
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Grant
Filed: April 29, 2005
Date of Patent: January 29, 2008
Assignee: Translucent Inc.
Inventors: Petar B. Atanackovic, Michael Lebby
Strain inducing multi-layer cap
Publication number: 20070018203
Abstract: A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.
Type: Application
Filed: July 22, 2005
Publication date: January 25, 2007
Inventors: Petar Atanackovic, Michael Lebby
Stacked transistors and process
Publication number: 20070018166
Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
Type: Application
Filed: July 22, 2005
Publication date: January 25, 2007
Inventors: Petar Atanackovic, Michael Lebby
Signal and/or ground planes with double buried insulator layers and fabrication process
Publication number: 20060246691
Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
Type: Application
Filed: April 29, 2005
Publication date: November 2, 2006
Inventors: Petar Atanackovic, Michael Lebby
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