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Re: alan81 post# 150726

Saturday, 11/23/2019 3:24:21 AM

Saturday, November 23, 2019 3:24:21 AM

Post# of 151682

Generally agree on the TSMC 7nm comments, however it is interesting to note that both the Apple A12 and the AMD chiplet are fairly small die at around 80mm, while the A13 moves up to about 90. The Icelake 10nm cpu is closer to 120 so INTC is manufacturing a larger die size on 10nm than TSMC is on 7nm.


I don't think you should conclude from two products on the entire process range. There are also FPGAs and GPUs made on TSMC 7nm, which are tiypically a lot bigger.

It should be clear, in general, that with increasing amounts of transistors, the likelihood of defects increases and therefore larger chips will face yields that are worse compared to a mature larger process node with the same chip size but half or less of transistors squeezed into it. Therefore the art of getting high end products from small as possible dies is what makes the difference. If Intel failed on that (I think there is more to it at 10nm though), it is still a fail. AMD saw this coming much earlier and their chiplet approach proves to be very successful. Also helps with yields and keeping different parts (with extra costs from foundries) low.

In terms of total capacity we can look at CAPEX as an indicator. Intel outspent TSMC in 2018 $15B to about $10B for TSMC. In 2019 they were about tied at $15B. Based on this I would expect them to have similar wafer capacity, if not more for INTC.


Certainly not. Wafer capacity from TSMC is way higher than from Intel. Intel sells products with much higher ASPs than what TSMC gets from its customers. No way Intel processes more wafers than TSMC. Not even remotely.

Icelake mobile clock rate is likely limited by more than process. They increased the cache size which may be the clock rate limiter. The GPU on icelake is a monster compared to previous mobile chips so that is taking a much bigger chunk of the power budget. With a 15% bump in IPC the sunnycove architecture looks very nice, but I do agree many will make a decision based on clock rate rather than performance.


How is an increased cache limiting clock speed? Have you had a look at how much cache AMD integrates on 7nm EPYC? It is huge and clocks are just fine. Intel has an issue with the maturity of its process, therefore they can't get enough yield for the fast corner, whatever the reasons are.
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