Tuesday, May 22, 2018 11:00:39 PM
XNRGI Battery Team experience in stacking design and testing for automobiles. (20nm stacking - 5 or 8 year old machines now ready for XNRGI) which other company could do Terawatt chip production for batteries...
GLOBALFOUNDRIES Demonstrates 3D TSV Capabilities on 20nm Technology
Apr 02, 2013
Fab 8 in New York delivers functional 20nm silicon with Through-Silicon-Vias (TSVs)
Milpitas, Calif., April 2, 2013 – GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GF’s leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.
TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers
GLOBALFOUNDRIES Demonstrates 3D TSV Capabilities on 20nm Technology
Apr 02, 2013
Fab 8 in New York delivers functional 20nm silicon with Through-Silicon-Vias (TSVs)
Milpitas, Calif., April 2, 2013 – GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GF’s leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.
TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers
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