bobide1$$$: Re: Spokeshave, do you have a clue from which stage of development this could be?
I can only go by what the company has told us. We know that:
The prototype that is currently being evaluated is a computer simulation. However, as I have pointed out before, the term "simulation" is a bit misleading. The only thing being simulated is the actual product. On other words, they have programmed a computer to act like an Embarq chip would. The potential customers evaluating this prototype would ostensibly plug it into their test loop and check to see if it really works as advertised.
This is a different stage of development than we were promised. The promise made as late as November of last year was that the prototype would be a Field Programmable Gate Array (FPGA) based prototype. By the company's own admission, they have not been yet able to produce the FPGA prototype.
Going from a computer simulation to an FPGA prototype is not trivial. It can, in fact, be very complex if the model is complex. With only 4 employees, and most of the money being raised by selling 144s going to pay Ray, Brad, Rich, and the rest of the board, there is little left over to actually work on the prototype development.
As long as I am speculating, I will speculate that the Fernandez technique is not incorporated into Embarq. Fernandez was given the scholarship by NVEI back when Cu@OCX was still in vogue. If he committed to work on something related to that, then well, he probably had to change his thesis mid-stream when he found out that the technology did not work. I doubt also that the guard interval paper that he wrote is a significant component of his thesis. What tends to happen in Ph.D. research is that you solve a number of small problems on your quest to solve your one big problem. I suspect that this is one of the small problems that Fernandez has solved along the way.
I cannot easily determine how much of an effort would be involved in incorporating Fernandez's work into Embarq. The math, though it sounds very complex, looks as though it would be rather simple to implement in computer code. The real qestion is whether it will actually represent a benefit in the real world. The paper does qualify the potential of the technique by saying: In particular this would make the system more sensitive to impulsive noise, a common impairment in the xDSL environment. So, it is not clear whether the technique will actually represent a real-world benefit.
Given unlimited resources, time and money, I would expect NVEI to develop an FPGA with many modular options, including Fernandez's tehcnique, that could be easily enabled and disabled to test their effectiveness in real conditions. Of course, we don't have those kind of resources.
Incidentally, I do have a question for anyone going to the SHM. I want to know exactly what that device was that they displayed at the last SHM. It was presented as though it were the development platform for the FPGA prototype, but it seems that is unlikely now. Someone please ask them what it really was.
