Advanced Micro Devices Inc (AMD)

[borusa]

SemiconEng, Thanks for not escelating the fud, I over reacted.

I don't have anything more than an intuitive guess, so...

Planerization, (as I understand it) would seem to be subject to the scale effect.

I should have stopped there, but here's another angle. Area for 300mm is ~2.25 * 200mm wafer. Assume that there is an optimal size for the current tooling. What might that be? Just on the face of it 200:300 is a large step and in a conservative model presumes optimum is higher.

Double the size of the wafer, compound that with double device dencity. As YB pointed out large caches may soak up that very expensive realestate.

I think it was noted in Bill and Ted's Excelent Adventure, "If such a thing as infinite smallness exists then infinite largeness also exist", can't have one without the other.