Advanced Micro Devices Inc (AMD)

[sgolds]

yourbankruptcy, on single vs. dual DDR & sockets -

Since there doesn't seem to be a published pinout, I tried working some numbers on my own. First, we see that DDR modules have 184 pins and DDR-II modules have 240 pins (unbuffered or registered DIMM modules), from p. 40 here:

http://e-insite.net/ednmag/contents/images/292200.pdf

Now, the difference in pins between Socket 940 and Socket 754 is (of course) 186. Since AMD has committed to DDR-II in future versions for both sockets that means that either

1. Socket 754 has some pins that are unused which are available for DDR 2 on Socket 940, or

2. Socket 754 and Socket 940 both support dual DDR.

Now, Opteron uses 16-bit HT connections between processors. This requires 103 pins per HT, or 309 pins total, per page 12 here:

http://www.hypertransport.org/docs/25012A_HTWhite_Paper_v1.1.pdf

(Note that each bit requires 4 data pins - full duplex and differential signalling.)

So here we have the following:

* Socket 940 has 186 more pins than socket 754;
* An extra DDR-II channel requires 240 pins;
* Two extra HT channels require 206 pins.

Hmmm... both are more than the socket difference of 186 pins.

However, I can make one firm conclusion: Based on these calculations, socket 754 must have enough pins to support either a second memory bank or a second HT.

I think we can infer from the roadmap that socket 754 will support dual DDR or DDR-II memory banks for future A64s. This is reinforced by the fact that A64 is never mentioned as a multiprocessed part (except for that curious paring with an Opteron, which would not require additional HT busses).

That is the only conclusion that makes sense to me: Unless someone can find fault with these calculations, socket 754 has enough pins to support a second memory controller, and this fits everything else that we know about roadmaps and processor plans.