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John:
I think you're right about the ton of money. But the objective was to ramp support for a memory technology. I'm sure they would have been satisfied with a smaller monetary return if they didn't have the Rambus debacle. Perhaps it was unavoidable but Micron seemed rather active in foiling Rambus acceptance.
I hope what ever objectives are part of this current investment are better aligned...
gb
I remember the last time Intel invested in Micron it didn't work out so well...
They gave them a pantload of money to spend on Rambus equipment which got spent "elsewhere"...
gb
deleted
sgolds: got it now. misunderstood.
tnx
gb
sgolds: No white boxes, either!
With your estimate of 400ku to sell and HP doing only a BTO SKU, AMD had better have a lot of white box folks lined up or they're going to be hurtin'.
How big an activity do you think HP BTO is? My guess is a pretty small percentage of their PC units.
gb
In any large employee population there are bound to be misbehaving members. It is quite possible that someone, somewhere, at sometime observed inappropriate behavior on the part of an Intel employee.
The question then to be asked "is such behavior condoned?" I can assure you that Intel trains it's sales and marketing personnel at least annually (typically more often) as to what behavior is legal vs. illegal and demands legal behavior be followed. The stated consequences of failure to follow is usually accompanied by words like "up to and including termination..." Does that mean some employee doesn't screw up? Nope. But it wasn't because they weren't trained.
But the legal standard is a pattern of explicitly or implicitly condoned behavior. That standard has found Intel without blame in spite of occasional allegations.
If you have proof of a pattern or a single example that you have personally witnessed of "behavior unbecoming" then by all means present it to the authorities. Babbling on about something that someone said or reported on a website somewhere doesn't help anyone make useful investment decisions.
gb
Keith
I'm sure the FTC would welcome your direct testimony in their investigation. Why not offer it?
I'm sure you do have direct knowledge to backup your allegation. Certainly you wouldn't make such an allegation on unsubtantiated rumors...
gb
my post was merely a reflection that if nvidia had anything else useful to do with a chipset group it would probably rank ahead of doing something for transmeta.
someone else very helpfully pointed out that nvidia can use this with their existing development of an htt chip until amd comes on line. good thought.
i seemed to have run over sgolds' puppy or something...
gb
i didn't take drjohn's reply as a rebuttal but more of a reinforcement that nvidia is looking for biz.
drivel? embarrassed? hardly...
gb
Looks like Nvidia has some slack time on its hands to be able to work with Transmeta. I take this to mean two things:
AMD ain't keeping them busy with the latest roadmap stretchout for the desktop into mid next year.
Nvidia didn't get an Intel bus license.
http://www.theinquirer.net/?article=11596
gb
Looks like Nvidia has some slack time on its hands to be able to work with Transmeta. I take this to mean two things:
AMD ain't keeping them busy with the latest roadmap stretchout for the desktop into mid next year.
Nvidia didn't get an Intel bus license.
http://www.theinquirer.net/?article=11596
gb
so we have a wide highspeed datapath that is supposed to be "bonded out" over multiple pin possibilities?
you must be kidding!
gb
re: guidance, opteron volumes and pricewatch listings.
to the extent pricewatch listings are from "approved" channels like authorized distributors amd no doubt has price protection in place and either can't count these opterons as sales out or must take reserves for priceprotection.
to the extent pricewatch listings reflect an opteron inventory buildup in "non-approved" channels then amd can chose to accept these as sales out and claim some momentum. but remember to what happened last year when amd had to go "clean up the channel"...
gb
sgolds: i understand how instruction sets and optimizations work. it is possible that amd's pipe and implementation of the instruction set is different than intel's and thus require different instruction scheduling. i was questioning whether amd had "optimizations" that required different instruction scheduling work by developers.
gb
Are the SSE2 optimizations unique to AMD? If so whose SSE2 implementation do you think developers will optimize to: Intel's or AMD's?
gb
the prescott pinout redo in the spring is to lay groundwork for a highvolume ramp of tejas the following year. this allows the folks building motherboards to make one socket serve both...as long as the specs don't change...
further they aren't pins, it is a new pinless package.
gb
Mike's response:
"That puzzled me a bit as well. I checked though... after. The Athlon 64 FX51, of course, launches after that day. That's the only interpretation I can put on it
Mike"
gb
interesting: http://www.theinquirer.net/?article=11385
i wonder if mageek misworded the article. it sounds like amd is exercising control through nda even after sept23.
i sent him an inquiry...
???
gb
chipguy: i about gagged on my coffee when i heard the 20% comment as well. to be fair he said "about 20%" which i assume included a generous amount of kentucky windage...
the reporter apparently was too far above his word count to include "about"... ;->
gb
Keith: that would be my interpretation...especially with the MS schedule comment.
i'm listening to the breakout session and rivet said "we're about 9 months ahead" of microsoft with a64.
gb
also rivet was very clear it will be "summer" before you'll see 90nm in the market...
gb
i listened and was surprised to hear that they are unwilling to say (or perhaps don't have a handle yet...) on what they are going to save as a result of the jv changes.
why wouldn't they know that and be able to share it two months after what should have been a thorough due diligence?
makes it sound like wishful thinking rather than good business planning...
gb
re: intel utilization
as recently at the q4 intc conf call bryant was mentioning that he was close to taking more charges for capacity under-utilization.
gb
If I read this right unless AMD goes foundry for 130nm bulk they will have three processes running simultaneously next year in Dresden:
130nm bulk Duron
130nm SOI for current Athlon and Opteron
90nm SOI for future Athlon and Opteron
non-trivial...
Apparently reality of 64bit everywhere (not) is starting to set in.
gb
i know him from meetings when i worked at intel. he's not a personal friend but i guy i very much respect.
he sounded a bit defensive in his lengthy rambling reply to the opteron competition question. could be just me...
gb
Anyone listen to Fister today?
Seemed a little defensive to me. I know Mike and he's just like he sounds on the telecon. He's a genuine guy...which had me a little worried.
Not much info on the roadmap...other than full speed ahead. Nothing new. Fair amount of discussion about "it ain't just a cpu" but lots of stack validation.
Q&A:
Some discussion about not depending on Serverworks, et. al., for platform feature like PCI-Express.
Some discussion about OEM adoption rate variations. NBD...
And of course the inevitable "Opteron/Yamhill" question which he deflected with a long discourse about everything it takes to make a server...not just addressing, etc.
gb
I seem to remember that 64 bit adders and multipliers were slower than 32 bit equivalents. Has there been any change in architecture that have removed these limitations? If not then speed limitations might be forcing a roadmap change for AMD.
gb
Anecdotally of course: I've recently bought two Centrino based Dell notebooks, a Inspirion 600 and a Inspirion 500. Both were shipped within a week of ordering. They work great!
gb
yeah, those vile underhanded intel scum had the nerve to begin building a compiler and tools team starting back in 1986.
gb
joe: packard bell died for some completely different reasons...imho, they were the enron of the pc biz...
gb
joe
last time i checked the chipset and resulting bios were different for amd vs intel. and the mb vendors *might* on a good day be second or third level backup but most of the time the oem has to become pretty expert in solving problems. that means cost.
gateway prior to ted returning lost their shirt trying to support amd and intel after ted's replacement (now gone) made a big stink out of no more intel only one time and went whole hog amd. don't you remember that? wasn't so long ago...
gb
support for another cpu includes different motherboard and its component bugs including base chipset, mb integrated peripherals, bios and drivers. most vendors support these things for 2-3 years after introduction.
it's a big deal when your margins are dependent on no calls.
why do you think oems prefer "universal" motherboards?
gb
Not really a defense. Just facts to help folks make investment decisions. Bad assumptions about pricing could make for bad investment decisions.
Pricing is much flatter than you apparently realize. Steep pricing usually leads to flattening via the grey market as OEMs become "distributors."
Reread my comments regarding "special pricing". Robinson-Pattman results in any OEM who can serve the identified opportunity getting the same pricing or incentives.
Dell's biggest advantage is having no inventory and consequently immediate ability to respond to market changes.
gb
I understand pretty well what IBM plays here: Let Intel pay for NOT offering Opterons in the segments where the money is by delivering Xeons for fractions of listprices; enabling IBM to attack the DELL-territory.
You have an implicit assumption about Intel pricing that is incorrect. Intel has very flat pricing across customers, subject mostly to volume, due to Intel's market position and the Robinson-Pattman act.
Pretty much everyone with the same volume gets the same price. The concept of "special Dell" or "special IBM" pricing just doesn't exist. Special prices are possible to address new markets such as some identifiable market segment not being served but such deals would be offered to any OEM capable of addressing that market and would be subject to marketing and volume conditions being met.
Google "Robinson-Pattman" for more info.
IANAL...
gb
National layoffs: the press release I read this morning indicated they would still need to layoff 65 people as AMD wouldn't be taking them all.
gb
sgolds: the selector sounds like segmentation. i know all about that.
gb
wmbz: agreed. eom
wmbz: pointer
so the os gives you a 64 bit pointer ulonglong but your software is written for ulong = 32 bit pointer. it's nice that a64 doesn't gratuitously retype your pointer for you but you still need to do a bit of a rewrite and debug to make sure you're mixing 64bit and 32bit pointers don't you?
not just a recompile...
gb
so how do you access the space given? with 32 bit pointers or 64 bit pointers? the os has to give you a buffer pointer doesn't it?
gb