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Newest K8s have 1GHz as bottom frequency. Versions from a year or so ago use 800MHz instead.
Regards,
Rink
Chipguy, re: You missed the simplest and most obvious (except to bashers I guess) - high margin chip and system sales growing rapidly and access to computer markets that historically rejects x86.
The IPF growth isn't enough to make up for the decline in high end legacy PA/Alpha/MIPS systems.
Regards,
Rink
Wbmw, Might be wrong but I remember that Intel has 8 way associative L2 as of Pentium III until now. 8 way is only one step from the 16 way associative L2 that AMD implemented as of K7 and maintained till now. Another difference is that AMDs L1 and L2 are exclusive, while Intel's L1 and L2 are not. Intel's L2 is way more dense but has a bit higher latency. AMD uses more computing units than Intel in their cpus (9 issue) up till now too.
There's so many different factors that it's hard to determine why 16 way for AMD is the optimum, while 8 way for Intel is apparently their optimum. I remember that at the time K7 with L2 first became common I read some very detailed tests that showed that 16 way associativity was a good thing for K7.
FWIW, Regards,
Rink
Buggi, could you please post a link to your WO post? I'm interested in your german comments.
Regards,
Rink
Kate, wise up please. "paranoid symptoms" != "paranoid".
Besides I agree with mas that "accusing retired IBM employees of working for AMD" can be a "symptom of paranoia". I'm not qualified in that area so at this point I might do well to suggest a doctor?...
Regards,
Rink
The I2 blades were about done before Hurd entered the picture. The only question for him was whether to release it or not (development costs were already made). The more I2s sold the better for HP. They need I2 at this particular moment to counter Power, and to a lesser extent Sparc.
Regards,
Rink
Kate, funny, I've got a BS in BM too, plus BS in Electronics. Majored in Total Quality Management, and Electronic Computer Integrated Manufacturing. Company training includes several software designd, development and quality management courses. Mostly worked for a large US IT company as well.
Regards,
Rink
( deleted; wrong place)
Kate, just curious, what did you study?
Kate, you're not implying to have a great mind yourself, are you?
Keith, re: Yonah, a 65-nanometer dual-core notebook chip, will go into volume production by the end of the year, he added. By the third quarter of 2006, more chips will be produced on the 65-nanometer process than on the 90-nanometer process, the so-called cross-over point.
You know this is very likely to be a wrong interpretation of the crossover talk during Intels CC.
re: "I'm guessing it (65-nanometer production at Dresden) will happen closer to mid-2006," said Nathan Brookwood at Insight 64. "Second quarter 2006 if they are lucky, and third quarter if they aren't."
This is an old Brookwood quote from about a month or so ago. It is clear this isn't exactly the brightest of authors.
Regards,
Rink
Wbmw, thanks! (eom)
Klaus, duh, I misread your statement. It seems that what you're saying is actually quite close to what we said. Sorry about that.
Regards,
Rink
Klaus, re: While I did not yet listen to the call.
You don't know what you're talking about. What Buggi confirmed was in line with what I heard, so it is rather likely to be the truth (65nm crossover for the performance segment Q3 at the earliest). Maybe you can listen to the call too; that might add some more details to this discussion.
Regards,
Rink
Chipguy, wbmw, I'm not sure about the current status of the below 300mm facilities. Could you please correct me where I'm wrong?
- Hillsboro, Oregon, fab D1C, 90nm
- Hillsboro, Oregon, fab D1D, 65nm
- Leixlip, Kildare, Ireland, fab 24, 90nm
- Leixlip, Kildare, Ireland, fab 24-2, still under construction?, 65nm.
- Chandler, Arizona, fab 12 is being converted from 200mm to 300mm 65nm.
- Chandler, Arizona, fab 22, 130nm
- Albuquerque, New Mexico, fab 11X, 90nm
Also which of the 90nm fabs is still going to be converted to 65nm?
Lastly is intial 65nm production coming from fab D1D or fab 12?
Thanks, regards,
Regards,
Rink
PS, The above info is from several articles I kept. Just found it is nicely aligned with this nice summary (don't know what the date is from this pdf; I think I saw it a year ago as well): http://www.intel.com/pressroom/kits/manufacturing/manufacturing_at_a_glance.pdf
Buggi, The analyst was questioning Paul about a previously mentioned Q3 for 'crossover for performance'. So the analyst mentioned Q3 (not Paul fafair). I didn't hear Paul denying this. He might well have replied 'end of 2006' but I'm not sure about that. I am sure however that they spoke about 'crossover for performance', and definitely not 'crossover for all cpu production'. Thanks for confirming that it it was crossover for the performance segment.
Regards,
Rink
Buggi, re: Paul said AGAIN this CC, that the crossover will ONLY!!! appear at the performance segment.
Did you hear this yourself? I also heard something like this on the call but wasn't entirely sure of how to interprete it. What I heard was 'crossover for performance' in 'Q3'.
Regards,
Rink
Fujitsu Will Offer Opteron-Based Server (blade) http://www.eweek.com/article2/0,1895,1872455,00.asp
Regards,
Rink
Chipguy, G, apparently you need some explanation as well.
The Opteron 875 based systems in general, even though the AMD asks very high prices for it, are a "relative" "steal" compared to price/performance of similarly configured or similarly performing Xeon MP systems. AMD did better in the 4 socket server segment than any other server segment specifically because of relative price/performance compared with competition. This was already the case before AMD introduced DC Opteron. During this quarter while Paxville gets offered more in shipping systems Opterons prices might well be cut to better match the changed competition. Those price cuts are likely to take into account the additional performance offered by Opteron compared with Paxville to an extent. Another price re-evaluation will take place when Bensley hits the market. Then somewhere close to the end of next year another one because of Woodcrest.
So currently though in absolute terms the DC Opterons are expensive in relative sense they are a steal. I never said anything different.
Regards,
Rink
Wbmw, well apparently truth is an absolute only few people grasp sometimes even though most think they do most of the time.
Yes I've bet against the odds and thought/think powerful Intel is just not powerful enough to prevent AMD from taking marketshare for at least a whole year. So far I've profited a lot from this thinking, partly because I often do not participate in major declines with relatively risky money. My long term position does get a hit but also recovered always so far.
Regards,
Rink
Chipguy, Not sure I fully understand you. Are you a fan of the communist ideals? Fwiw, I'm more of a capitalist myself. That's actually why, although Intel is by far the most powerful of the two, I still invest in AMD.
Regards,
Rink
Kate, guess again. Because you're so great here's a hint: It's relative.
Regards,
Rink
re: So how much is the gross margin on those $2149 DC Opterons? Is that "robbing customers" as well?
No, they're a steal.
Regards,
Rink
PS, everything's relative.
Keit, fully agree with both your arguments as to why AMD went down (as well). Even think I stated both of them already to an extent:
8: Added depreciation in Q1 on very little added volume == Rivet stating H1 '06 is a little difficult from a cost perspective.
10: Profit taking == your valuation argument.
Regards,
Rink
Keith, I can't make sense of it either. Here's some incomplete reasons all of which might added a bit of uncertainty for different groups of people. Once the downward movement started these slowly became known to more people which enforced downwards pressure.
1. Maybe some people knew 65nm would be delayed.
2. Fab 36 a bit later on line than some of the optimists expected.
3. The amount of diluted shares was higher than many had anticipated.
4. Close to $66M profit sharing.
5. Investors were advised en masse to hold into earnings and got spooked when earnings results didn't match price pressure.
6. Intel intro's great many new chips start of Q1.
7. R&D+OpEx guidance a tad higher than some expected.
8. Q1 will see some added depreciation on little added volume.
9. AMD always goes down after earnings.
10. Earnings peaked while 2006 is unclear => it's time to profit now.
It's only a somewhat reasonable theory. The only reasonable one I can come up with considering the info available. Although I'm with you and still looking for the real explanation I also think this is a reasonable enough that it could have happened like I described. For example on SI it took us some time to figure out some of these items too.
Regards,
Rink
Keith, AMD reported that it growth in emerging markets exceeded its growth elsewhere. Also that their ASPs in emerging markets are rising faster than their ASPs elsewhere but that it ofcourse comes from a lower ASP base to start with. FWIW.
Regards,
Rink
Smooth, Charlie mentioned that rev F includes support for quad core, DDR2, and the 'next spin' after initial rev F will include PCIe on die. We're only likely to see DDR2 with rev F cpu's activated and shipping end Q1 for systems in Q2.
A next completely redesigned core isn't due till H2 2007. It's refered to as K10.
Regards,
Rink
Joe, Doug, talk of 3.8GHz was only for Dempsey. Pressler talk was 3.4GHz.
Regards,
Rink
TMF: Don't Count AMD Out Yet http://www.fool.com/news/commentary/2005/commentary05101315.htm
Nice article. Here's one piece that breaks AMDs potential down in laymans terms:
The best proxy may be the second-quarter numbers. According to Mercury Research, AMD came in at $758 million in x86 processor revenue, or 10.3% of the total. Intel, conversely, had $6.6 billion, or 89.3% of the market. There were also roughly 55 million x86 units shipped during the quarter. Mercury pegs Intel's share of those shipments at 82.3%, while AMD accounted for only 16.2%.
Now, couple these data with the projections made by AMD CEO Hector Ruiz in his interview with trade publication InformationWeek. In it, he says that AMD hopes to garner 25% to 30% of the total x86 market by 2008 or 2009, which he estimates to be at least 400 million units. (Interestingly, that would also be double 2004's record 200 million in shipments, according to Mercury.)
Got all that? Good. We now have all the necessary pieces to make a rough guess at AMD's total 2009 market opportunity. Here's the breakdown:
- If AMD grabbed 16.2% of the market in Q2,
- and that market totaled 55 million units,
- then AMD likely shipped 8.9 million units,
- and if those units totaled $758 million,
- then AMD's per-unit sales were probably $85 or thereabouts.
If that pricing stays roughly constant, then Ruiz's 100 million shipments in 2009 would result in $8.5 billion in sales. AMD booked $3.2 billion in microprocessor sales over the past 12 months. Do the math, Fool, and you'll find that AMD expects to at least double its processor revenue over the next four years, if you were to assume base projection on market share estimates, and more if we were to employ the assumptions of constant pricing and Ruiz's unit assumption. And this is a stock that's overvalued?
Regards,
Rink
Wbmw, re: 2006 is Intels turnaround year because of Yonah, Sossaman, Pressler, Dempsey, Cedar Mill and Montecito?
- Yonah: Likely very succesful notebook chip.
- SossamAn: Niche server blade chip based on Yonah (niche because of lack of 64b)
- Pressler: 65nm Netburst
- Dempsey: 65nm Netburst
- Cedar Mill: 65nm Netburst
- Montecito/Montvale: 90nm Itaniums. There isn't going to be any 65nm Itanium chip in all 2006 (that's what Montvale was supposed to be until Intel backtracked and said Montvale will be 90nm). Montecito's frequency slightly disappoints. Montvale's frequency disappoints massively because of the before mentioned reason. Still, top notch performance is very likely though to allow HP to continue the move to it from legacy chips.
The 65nm Netburst chips ain't going beat Opteron/Athlon64/X2 and you know it. Sossaman is for the 32b niche in the blade server market. Montecito/Montvale are very unlikely to slow x86 server sales growth.
Hence you're statement that 2006 is a turnaround year for Intel won't become true till Merom/Conroe/Woodcrest at the earliest.
BTW, I sold 60% of my Jan 20's when the common was just under $26. The other 40% is unfortunately worth now what I bought it for originally. Just bought some more '07 leaps.
Regards,
Rink
Chipguy, Montecito not to exceed 1.6GHz / 18MB L2 in Q1 '06. Q2 will see the introduction of the top of the line 1.8GHz / 24MB L2 chip. At least according to here: http://news.zdnet.com/2100-9584_22-5894081.html
Regards,
Rink
LOL! Don't make me question your hair color... (eom)
Doug, can you please leave this blond alone to admire whatever qualities she thinks she has?
Thanks!, regards,
Rink
Mike, don't they distribute Turions or am I perhaps missing something?
Regards,
Rink
Pete, re: Cedarmill isn't supposed to be released until Q3/06
Are you sure?? Somewhere in the back of my head I had it due for end Q1, start Q2, certainly not Q3.
Regards,
Rink
Kate, Don't bother. It would rather likely would show exactly the opposite.
Regards,
Rink
Chipguy, re: Well, yes and no. See Hans De Vries disection of Prescott die: It's two 32b ALUs working in conjunction for 64b calculations.
Your reply: If that was true it would have half the throughput for 64 bit integer operations as it does for 32 bit operations. I have not seen any indication of that in Intel's x86 optimization guide.
Here's how I understood it: Throughput is the same with 64b as for 32b. The double frequency 32b ALUs work in conjunction with each other. The reserve bit (as we call it in Holland; hope my translation works OK; the 33rd bit) of the lower 32b add in the first unit is past on to the second ALU that calculates the higher 32b result. The full 64b result is available in 50% more time than takes for a 32b add. Throughput is the same however, because every half clock a new 64b add can be started (same as for 32b adds). Or in other words 64b adds can be started back to back every half clock(same as for 32b adds). Note: I took an add as example only. The same goes for other simple INT calcs.
Hope my words make sense to you as I'm hardly an expert. This is how I interpreted what I read from Hans de Vries. I fully believe his analysis as it has not been contradicted once to my knowledge. I did keep an eye out for contradictions; they never appeared.
Regards,
Rink
From the links I provided:
Second integer core for 64 bit processing (not for multithreading)
It is as good as sure that the second 32 bit core is exclusively used for 64 bit processing, and in a way similar to the good old bit slices. ... The fact that makes it possible is because the core's is limited mainly to additive and logic functions. A 64 bit staggered addition will take a total of four 1/2 cycles but you can start two of them back to back on 1/2 cycle intervals. The higher part of the address is only used several cycles later to check the address tags with the TLB entries and not to access the data cache itself. What will increase with one cycle is the latency from an ALU instruction to a normal speed integer instructions. This delay will increase from 2 to 3 cycles. One extra pipeline stage is needed as well, resulting in a minor increase in the branch miss prediction penalty.
And:
Kate, can you explain where exactly K is 'wrong'?
Regards,
Rink
wbmw, re: The Prescott ALUs seem to have been designed from the beginning to be 64-bit.
Well, yes and no. See Hans De Vries disection of Prescott die: It's two 32b ALUs working in conjunction for 64b calculations.
Die photo, INT section enlarged: http://www.chip-architect.com/news/2003_03_26_Prescott_clues_for_Yamhill.html
Final conclusion (2x32b): http://www.chip-architect.com/news/2003_04_20_Looking_at_Intels_Prescott_part2.html#Second%20integer...
My guess has been that this two times 32b ALUs might have been planned from the beginning to allow flexibility to never use it, or when it would become necessary to have 64b Int calculations. Just my take on Intel's implementation of 64b extension. Take it for what you think it is worth.
Regards,
Rink
Wbmw, re: AMD and Intel production processes.
Re: I didn't marginalize [the SOI and better strain] features of AMD's process
You did. You still do.
Re: Strained silicon is a benefit, but compared to what?
That's not relevant question, as this question should have refered to my statement that current AMD's strained Si is has BETTER than Intel's (performance and power wise).
Re: Yes SOI is costly, and it affects yields! I'm glad you recognize it in this response...but it didn't stop you from calling Intel's low-yielding earlier.
That's another subject, plus I don't recall mentioning this either. I do recall questioning you a while back if you had data for your factless statement that Intel has better yields than AMD. That statement is still factless. You never showed the data, or claimed you had any for that matter. So why make a statement like that?? Anyways, I also think Intel's method strain causes more yield loss compared with AMD (for this I have no data though. Back to the current discussion.
Re: I say part of the reason Pentium M reaches such low power is not because AMD's process sucks, but because Intel's process is very good at delivering high performance and low power if the design is done the right way.
I stated that 'Intel has a good process', but question if it's the best. I clearly think not, and base my conclusion on facts. You almost never show data or facts regarding this type of discussion and this is no exception. Surely SOI and better strain are facts that do support the notion that AMD has a better process. You in fact have no significant facts at all. Pentium M is designed for mobile ONLY (K8 was designed for servers first). Pentium M's current FP performance is mediocre, and even it's INT performance is not leading at all. So your conclusion that because of Pentium M is performing OK Intel's process is the best is flawed.
re: I have also asked you to refer to public data on the drive strength vs. leakage of Intel's process vs. AMD's.
You did not; especially not in this discussion. I saw the graphs though a while back. I found them impressive but apparently without any consequence whatsoever. So far slidewear.
re: I have repeatedly pointed you to the fact that Prescott was a frequency driven design with high power transistors used throughout
Yeah, so? Everyone knows. It's a bad design for Intel's current process.
As for Montecito, the same source that claims it will be lower frequency (The Inq) also claims that engineers have been taken off the design to fund Xeon design teams, which would explain why the design would fall short of target.
Bla, bla. Montecito's design was cast in stone before the engineers were asked to join mainstream cpu design teams.
re: Lastly, Dothan now clocks as high as 2.26GHz at a 27W TDP, which is 33% higher frequency than Banias at 1.7GHz and 24.5W TDP. That's not a bad boost for a power constrained design.
Dothan is not Banias; they're two different designs EVEN though Dothan is to a good extent a shrink of Banias.
re: Aspects of APM involve transferring process steps exactly from the development fab to the production fab... That's a fundamental similarity to Intel's Copy Exactly. My point was that Intel's methods for automation do the same things as AMD's APM, and they have been in place for years.
Yeah, yeah, minor aspects. APM has in general terms nothing to do with Copy Exactly. Considering your reply you probably even know that by now. APM is rather broadly patented, and AMD is recognized for leading in this area by the industry. Your words that "AMD copied Intel's Copy Exactly" show exactly how little you know about this subject.
re: I see that you will argue for SOI and DSL until you're blue in the face, without showing a shred of proof. Not that it matters, because the results will speak for themselves.
SOI and DSL are facts. You have none.
Rink: I'm not going to bother with your other statements. Maybe someone else will.
Wbmw: Sure, you are free to toss out FUD on Intel's process, and when someone confronts you with it, you start pouting like a little girl.
It would probably have been pointless because I'm talking to you.
Regards,
Rink