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Very little change since Vilfred Pareto noted in 1906 that twenty percent of the people own 80 percent of the wealth
so you think bottom 80% ownership getting halved in a century is very little.
by your definition with another very little change the percentage could go from 90 to 100 and top 20% could own everything and we would be back in medieval times
"The problem with socialism is that eventually you run out of other people's money," Margaret Thatcher once pointed out.
Not likely; top 20% percent own almost 90% of the wealth. What do you suppose we do with the bottom 80% ?
Total Net Worth
Top 1 percent Next 19 percent Bottom 80 percent
1983 33.8% 47.5% 18.7%
1989 37.4% 46.2% 16.5%
1992 37.2% 46.6% 16.2%
1995 38.5% 45.4% 16.1%
1998 38.1% 45.3% 16.6%
2001 33.4% 51.0% 15.6%
2004 34.3% 50.3% 15.3%
2007 34.6% 50.5% 15.0%
2010 35.4% 53.5% 11.1%
http://www2.ucsc.edu/whorulesamerica/power/wealth.html
Intel Corp. has decided to delay mass production of its next-generation code-named “Broadwell-E” microprocessor to the first quarter of 2016. Exact reasons for the decision are unclear, but probably the issues with the company’s 14nm process technology as well as the lack of competition on the market of ultra-high-end desktop platforms are among them.
http://www.kitguru.net/components/cpu/anton-shilov/intel-delays-broadwell-e-processor-for-high-end-desktops-to-2016/
this is one of the best examples of "sometimes you bend over backwards so much that you fall flat on your face."
the bottom line is at the moment intel is paying $15 to the oem to use intel's $15 chip. no amount of twisting, wiggling and bending over backwards to "explain" it won't change that fact; but i must commend you for trying so hard ...
nexus 9 has nvidia tegra k1 (64 bit).
I was mainly arguing against this:
a lot of swapping still needs to take place between the L1 cache and the registers
with extra registers internally, there is no need for L1 interaction as the extra registers define another memory hierarchy between named registers and L1. Just as updates done to a memory location can just stay in L1 and not written to memory, an update to a renamed register doesn't have to get propagated to L1 (nor memory (except any coherence issues of course))
register renaming, ... isn't the same as having more architected registers
when was that claim ever made in this discussion?
You'd rather have the latter
well, duh.
a lot of swapping still needs to take place between the L1 cache and the registers. This is because the assembly code itself does not have access to the large register file that register renaming provides for. Otherwise, the assembler can just store data within registers, leave it in there for a bit, then access them later on without having to write it to memory.
i am not sure if this is the forum for this but this is really not true. with extra registers, the data doesn't have to get to l1 or memory, as they define an extra layer in the memory hierarchy between named registers and l1 cache just as not everything in the l1 cache has to go to memory.
But trace caches have little to do with CISC vs. RISC. Both can employ trace caches, and both can get performance benefits thereof.
as they allow the processor to bypass the decoder, trace caches give a much larger benefit to a cisc, especially not as thorny as x86.
there are limitations in the x86 ISA itself such as a small number of architected registers. This causes the assembly code to swap a lot of data between the registers and the L1 cache, which represents wasted cycles that RISC ISAs typically don't have to do.
there are two ways to get around this: register renaming. the risc processor inside an x86 implementation today has many more registers than the limited registers (ax, bx, ...) and the processor keeps track of which registers can be duplicated internally by checking dependencies on instructions. so many more instructions can be in flight with their independent registers even though externally they seem to use the same register.
the second is a trace/micro-op cache(s), which is one of the more mysterious beasts. this block actually caches the generated micro-ops and the processor can run strictly out of the cache without doing any instruction fetches, decoding, micro-op generation at all. trace/micro-op cache is one of the more recent inventions and a beauty in its complexity
Apple 12-inch tablet may adopt Mac OS, iOS-integrated operating system
maybe yes, maybe no.
http://www.digitimes.com/news/a20141001PD203.html
Intel's Broadwell U series will enter mass production in January 2015 and begin mass shipments by the end of the first quarter 2015. The high-end Broadwell H series will become available in the third quarter of 2015.
Following Broadwell, Intel will release its next-generation 14nm Skylake series and the processors will enter mass production in the third quarter of 2015 at the earliest.
skylake it is.
http://www.digitimes.com/news/a20141006PD207.html
Tesla Said to Join Luxury Race Into Automated Driving
http://www.bloomberg.com/news/2014-10-03/tesla-said-to-add-popular-automated-driving-functions.html
There might also be a small advantage in power consumption, but that's theoretical and based on the whole notion that RISC is inherently better than CISC.
actually if you look at the actual execution engine of a high performance x86 cpu these days, you would find that it is a high performance risc processor. the decoder is the only block which needs to see the cisc stuff; after that everything is converted to micro-ops which are risc. decoder is less than 5% a high end cpu so power savings of arm is only valid for very low power cpus where decoding would consume a larger relative portion of the power. At 50+ watts it is not a differentiator.
ExaGear enables running of x86 Linux applications directly on ARM based Mini PCs simultaneously with native applications
interesting, eh? i wonder what the performance is like.
http://eltechs.com/eltechs-has-launched-exagear-desktop/
q: how many legs would a horse have if you call a tail a leg?
a: 4. calling a tail a leg doesn't make it so.
Intel will launch its 14nm Y series Broadwell processors in December and start mass production in February of 2015.
h parts are due for q2. skylake is looking more and more like the avenue for my upgrade.
http://www.digitimes.com/news/a20141002PD207.html
Vendors stop developing touchscreen notebooks
http://www.digitimes.com/news/a20140929PD205.html
The weak demand for touchscreen notebooks is greatly impacting Intel and Microsoft, both of which have been aggressively promoting the touch functions on notebooks
The sources pointed out that vendors are now placing their hope on Windows 9 in 2015 and hoping new hardware or software innovations will stimulate demand
Cadence Unveils Broad IP Portfolio for New TSMC 16nm FinFET Plus Process
Silicon-tested IP is expected to be available beginning in Q4 2014
http://www.prnewswire.com/news-releases/cadence-unveils-broad-ip-portfolio-for-new-tsmc-16nm-finfet-plus-process-277234201.html
Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Both Companies Enter 10-nm FinFET Collaboration
http://news.synopsys.com/2014-09-25-Synopsys-Tools-Achieve-TSMC-Certification-for-16-nm-FinFET-Process-and-Entered-10-nm-FinFET-Collaboration
TSMC Delivers First Fully Functional 16FinFET Networking Processor
http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=8821
it would not give them complete control over their system. i am not suggesting at all that they would do x86 emulation nor they would completely switch away from x86. i am just suggesting that it makes sense for them to have another platform between iphone/ipad and macbook which runs an arm mac os port without x86 compatibility but with ios compatibility. the first indication of this would be if they supported ios apps on mac os. i am just speculating that bringing the oses closer and especially letting mac os run ios apps would create another platform for them. there is no reason ios 9/10 can't carry more desktop productivity type apis similar to mac os. it's not a binary 0/1 approach anymore. they already have two platforms and it only makes sense to bring the one they own closer to the one they don't.
I strive to
the only thing you seem to strive looks like calling people names when you don't have a good argument.
what advantage would that gain for Apple
a $10-12 cpu compared to a $100-150 cpu?
how come Microsoft failed with Surface RT? It should have been a hit given the advantages ARM brought to the platform, right?
it runs windows. not even the full version. even ms didn't port all their own software to it and they don't own the cpu either. there is no comparison.
Spoken like a weasel analyst.
great comeback, very thoughtful and insightful; congrats.
btw instead of name calling an analysis of how mac products are doing is in order. do you think people are buying mac notebooks in large numbers because they want to run "productivity" applications on them ? even if that's the case, those "productivity" apps are not as much ms office and such but the apps one can get from apple. how difficult would it be for apple to make a 12/13" a9 based notebook which has all their apps installed on it ? even though it doesn't run x86 apps, what percentage of the macbook market do you think it would grab?
I wonder for what the top half of the chip is responsible. There seems to be a lot of IP with its own SRAM. Also it seems like, if one cared, this chip can be compacted another 15-20% but taping-out A9 probably takes precedence over that.
I wonder for what the top half of the chip is responsible. There seems to be a lot of IP with its own SRAM. Also it seems like, if one cared, this chip can be compacted another 15-20% but taping-out A9 probably takes precedence over that.
I just don't believe they are the same product
they may not be the same product but the money people are spending on them is the same money. people seem to be moving away from the heavily subsidized phone to buying it and how many $700 devices can you buy.
of course this is not everybody. some people still need/want a notebook (i do for example) but the trend is not in that direction. i see more people every day in peet's typing on their tablet/phone than with their mac book.
as for me i am pissed that i have to spend >$1500 on a decent notebook and still no broadwell. my 17" ib notebook is still waiting to be upgraded.
How long ago was ChuckD predicting this?
it only needs to happen once ...
A Mac OS port would be expensive and complicated and filled with painful driver/compatibility issues. Do you really think Apple wants that right now?
depends on how long they've been working on it. it's not as if they have to accept drivers from third parties. also depends on how much margin improvement they would see. broadwell u parts seem to have a $100+ price (if not $200+). a8/a9 cost to apple is probably no more than $10 (~c8/mmsq + $3 for test+package).
all speculation of course.
it is assumed that Intel’s Broadwell processor
an a8/a9 will also allow a fanless notebook too
an example from 7 (8?) generations ago to explain today's problem, eh? smart...
of course without specifics this is meaningless nonsense. one could have less cache and be more io bound so density would be significantly lower of course. it shows nothing about the density of the logic transistors which are the overwhelming majority of transistor in today's socs/cpus.
the real test will be when intel finally announces a 14nm soc. any bets when that's going to happen?
i take my notebooks with me all the time. i still have a 17" 1920x1200 mbpro which i occasionally use for layout.
the all in one is interesting but it comes with crappy cpus and crappier display. who needs a 19.5" display with 1600x900?
looks like my sb notebook upgrade will pass over bw too. i do wish they have 17" high resolution displays by then. where is that 17" mbpro?
a8 vs core-m transistor density!
it seems a8 has ~2B transistors and die size of 89 mmsq (http://www.anandtech.com/show/8504/apple-announces-a8-soc)
core-m on the other hand has 1.3B transistors on 82mmsq (http://wccftech.com/intel-14nm-core-m-broadwell-y-processors-detailed/)
this gives a transistor density of 22.5M/mmsq and 15.9/mmsq for A8 and core-m respectively.
So unless my numbers and/or math are wrong A8 at 20nm is 42% denser than Core-M at 14 nm.
Maybe the payment thing is a big deal?
in terms of apple's inserting itself into consumer purchases (taking a cut, data collection etc) that could be a very big deal.
A 4 d printer?
why not? a statue which changes over time would be awesome.
tim can't be held responsible for what he says. phud is the one who started "liberals are ..."
No need to get personal
actually there is, as you are the one who start the political bullshit (at least this time)