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Seconded. The most certain sign for a moron is calling others so. K.
spaarky
What i posted to Alan was something else, (Nehalem/GPU).
Wrt to Intels fabs, I can't speak for others. I have not seen the change in fabcount covered in public commentaries yet. Everyone might have her/his own reasons not to highlight it, an oversight is just one possibility for this.
Also, a step backward is not how i understand Intels move. Rather a step to deliberately make things more costly to apply more pressure on AMD. Nothing wrong with it. 3B for another fab does not cause any headake for Intels management. But it does for AMD's to follow it.
K.
Then maybe you should treat the things told to you in confidence by not posting obliquely on a world-wide investment message board. Eh?
Many thanks for any education what i should do and what not. (This goes for elmer as well where is should be and where not).
The tidbit i posted to Alan is no trade-secret at all, but common knowledge. Just not communicated on PR-slides, as it seems. Not surprisingly, it is nothing to make a story of, but just a reasonable implementation. I would not even be able to remember when i heard this first from, nor from whom - in fact I could not think of anybody familiar with it who would portray it differently.
K.
It best you at least let us know that persons capacity. Who do they work for, and what has been their historical veracity. The more details you can provide, the more credible it will be.
I see the concept. Best would be full name and rank and a phone-number to confirm. This might work - once - but only if somebody with a sane mind would tell somebody with this concept anything beyond the actual time. From experience, this is not so.
K.
you'll be greeted with the internet equivalent of rotten tomatoes.
While i am not sure you are aware which part of the population's typical behaviour you describe, i would not argue you have a point here.
K.
if you haven't noticed yet, without a reference or link nobody's going to take you seriously and they will think of you as a clown. It's unfortunate you've chosen that persona.
I could not care less. If you haven't noticed yet, i never did and never will subscribe to the idea link-references are sources of ultimate wisdom.
K.
I wouldn't count on AMD's outsourcing partners to help them to ramp a competitive process, if AMD themselves cannot do it in their existing fabs.
Are you assuming AMD has an existing 45nm fab to do it there?
K.
Have you read any direct references to Intel's 45nm being poor yielding anywhere ?
No, i did not read it. [sic!]
K.
This is a misunderstanding. I said no link. I did not say no source. K.
Many thanks - valuable contribution.
See my reply to Ronster why.
K.
Appreciate you don't even try arguments to save time.
Hats off. I could not think of a more efficient way to communicate your stance.
K.
wbmw
Feel free to read this into the statement. It is not in it, though.
K.
It's not a "bad process" - just a sacrifice Intel deliberately chose to give.
K.
wbmw
I was very clear on this already.
1. Intel said it will be three fabs in 45nm until recently.
2. Then it announced metal gates in this node, and by the same time changed communication to four fabs.
Not more - not less.
Besides, metal gates are known to be a manufacturing challenge. The relevant publications are not publicly available on the net, at least not without subscriptions. So I cannot link to these.
On a sidenote, i do not even think about accusing Andy Bryant for lying or being overly optimistic with his three fabs portrayal. I take this as Intel apparently changed plans. They are allowed to whenever they want and as often as they want. Same goes for AMD, naturally.
K.
AMD doesn't have a fab in Singapore, nor are they even planning one. Are you confusing fabs with assembly facilities, perhaps?
I am talking about Chartered Fab7. AMD has wafer-fabbing outsourced there already.
K.
Mike
I agree on AMD's sweet spot in the 65 nm parts
Umm, talking about "sweet spot" in this respect sounds like an oxymoron.
K.
we will just have to wait and see.
It's in the Chipset.
And there will not be a 45nm-chipset anytime soon.
(No link).
K.
Well feel free to take it so. Glad you bring back the idea Intel is always building an extra fab per node housing indoor-golf and spa for its management.
K.
Actually, we do know that with Nehalem both the MC and the GPU move onto the CPU, which changes things quite a lot.
Are you sure on the on-die-GPU for Nehalem?
Integration of IMC and CSI is known for long. The change in fabcount came by the time Intel announced to use metal gates.
K.
Sources
3 Fabs: From the top of my head, last i remember Andy Bryants comments in one of the recent Conference calls, i believe the one in January. Transcript is on seekingalpha.
4 Fabs: Recent Analyst Day presentation 07, the one from the chap talking about manufacturing, he did not leave an impression strong enough i remember his name.
I think you should really keep track on Intels fabcounts for leading-edge.
K.
Elmer
Did you think AMD was lying or just unrealistic when they claimed mid-2005?
Neither, nor. Their wording was ok, taken with a wink.
What do you thing about their 45nm claims?
Depends on whether they go into the node without metal-gates or not. I'd think it would be the better idea to start 45nm in Singapore rather than Dresden, and not even trying without metal gates. Which would put availability in mid 09 timeframe imo.
K.
It's just too bad that no semis are researching techniques that are viable in terms of cost and manufacturability.
All do. Howvever first you look for what works, and from what works you look what can be brought to manufacturability.
Metal gates work, and deliver benefits. But this does not come for free. It is the reason Intel added one fab from its plan of three 45nm fabs last year to four.
K.
AMD had nearly 1.5 years to resolve the "design issues" you mention.
Actually, no. They had a 300mm transition to make, i.e to qualify a completely new toolset for a new node. Only after the very last tools was qualified they could process a design migrated to 65nm rules. When they had silicon there was not much time to resolve what behaves different in data than in design-model.
Wrt belief, i called for Q1/07 availability of 65nm products from AMD since back in 04, despite what AMD said. It's on the record on ihub.
K.
wbmw
Do you know of any semis developing enhancements like this...?
Yes. The list of top twenty semiconductor-makers would be the answer to this.
Actually, there are dozens of improvements which work in the lab. The problem is not these don't exist, but their manufacturability. The other problem is the cost for leading edge nodes per se.
K.
Just for the record, your portrayal is overinterpreting my point of diminishing returns from migrating to smaller geometries by far. Besides, my understanding is that AMDs issues at 65nm are rather in design than in process. While it is kind of hard to distinguish because both are interdependent, the characteristics of products out there point to root causes to be resolved rather in design than in process.
I can't speak for pgerassi.
K.
Many thanks. Sounds faily compelling.
Looking at overall climate i find consoles trending weak as well as mobo tiers. Wrt the latter i'd think Intel is aggressive with Intel-branded boards currently to keep its revenues up in a softening environment, encompassed in its guidance.
K.
wbmw
Just came across your epscontest-entry for current quarter and wondered about the reasoning for the GM-drop on Intel-side you see. Did not find any commentary in the raw data. Could you elaborate what's behind it?
Tx.
K.
Kate
No dispute at all. I've seen it everywhere i've been, as well.
K.
Kate
Very nice to learn what Intel does when it is hiring. The case of talents unhappy with Intel is not very complicated: They look for another opportunity to do what they want to do, negociate a contract and leave. The more talent they have, the easier this works.
K.
Nicely put. I am not even trying to dispute anything of it.
K.
Scaling is also not 100%, more like 80% (2200 vs. 4000).
From the coverage i have seen yet AMD seems to struggle to get its message across here in terms of "scaling per watt".
K.
Kate
np. On a sidenote, folks i was talking about were working on CSI.
I am suprised you consider this the best of Itanium.
K.
Kate
they all decide.
Golly, where do you have that from? :)
K.
It's a lot, but eight channels would be needed to get close to parity, twelve to exceed it.
I look at Power6 memory architecture as targeted at large database-applications (large off-die L3, high-bandwidth i/o) while Tukwila as designed for its application-base of scientific/HPC apps where latency is paradigm. (Large on-die L2-caches). Insofar i am reluctant to compare the two arches at all, let alone parts of the arches alone.
I raised the question of Tukwilas CSI implementation mainly because i thought it could be a design which appears in Nehalem as well (Which i still believe will be so). Nehalem and K10 will play in the same league, so there comparison is due.
K.
But the middle and high level parts of CSI - semantics, protocols etc, won't. That is what defines a communications link standard.
I see. That's why PCI is still the PCI it ever was, i guess.
Why don't you do the SNR of this board a major favour and leave engineering to engineers.
Don't worry, i do. Probably you should as well.
Keep your comments up. They are funny at least.
K.
While i did not follow last year, i should have looked at tweakers.net first, naturally. Shame on me.
The question mark remains memory bandwidth.
4x FB-DIMM channels should provide ample memory bandwidth.
(Or do you mean CSI-data-path-width?)
K.
Just got what Intel says for Tukwila, although i do not fully understand it yet.
4 x 6.4 & 4.8 GT/s/dir full width. (Asynchronous??)
and 2x the above half width.
The implementation seems to be router on-die, controllers off-die from what i understood. If so, they could use this implemenation for Nehalem as well.
K.
these are the guys?
No, not these people.
K.
My point was that there's another reason why people may leave (or get reassigned)
Sure. Everybody's choice to read anything in when people leave in droves.
so they can start thinking about next-generation stuff again.
That is what they want - and what they do. Just not for Intel.
K.
Kate
Five in headcount terms is irrelevant for a project. Loosing five outstanding talents is significant. :)
K.