Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
I think Samsung is one U.S. government dumping investigation away
from being #4 or #5 instead of #2. And one Kim Jong Il misstep from
being off the top 10 list altogether. ;^)
chipguy, but did you forget to mention that IPF instruction set produces much bigger code than x86? Is
it twice or more, I don't recall?
That's about right. It will vary a lot. As a rule of thumb speed optimized RISC code is
about 40% larger than generic x86 code and speed optimized IPF code is about 40%
larger than speed optimized RISC code.
Keep in mind for trace cache based implementations of x86 that uOP code is 4 to 6
times bigger than x86 code. Unlike a P4, when an IPF processor like I2 takes an I$
miss it sucks in a 64 byte cache line in 5 or 6 clocks with no translation overhead. But
a P4 miss, in addition to L2 access latency, needs one extra clock cycle for every 3 to
4 bytes fetched to parse and translate the instruction stream.
Some occasional web posts I saw never were so positive about this instruction set as you are.
If HP was competing against Intel using EPIC processors manufactured by IBM instead
of being allied with Intel to commercialize this technology, EPIC would probably get much
better press on the web. :-P
I am not a particular fan of EPIC/VLIW, a clean RISC like Alpha seems like a better path
to take if only for the sake of simplicity, conceptual and implementation wise. But unlike
many technology enthusiasts on the web I recognize business and economic realities.
That reality is that IPF will take away most of the market share RISC currently enjoys in
high end commercial and technical computing machines over the next 5 years. Not because
it is a better technology, because it has a better business model.
Second, I am not convinced that complex, sequentially encoded variable length instructions and
addressing modes is a bad thing. Actually, since lines of memory are prefetched and then divided
into an instruction stream, the variable length of instructions is handled internally by the processor
concurrently with executing current instructions. No performance hit here!
No. In P6, K7, and K8 processors the critical execution loop has arguably two or three extra
pipe stages dedicated to the complexity of the x86 ISA and these have a relatively significant
cost in performance. The P4 eliminates those extra pipe stages but at a cost of blowing up
the instruction/trace cache size (increasing the miss rate per given amount of silicon area),
reducing its efficiency due to packing overhead and code duplciation, and penalizing cache
fills. Pick your poison.
I understand your position, but I disagree in several respects. First, the market for RISC processors
has grown over the past few years.
This is wrong. The market for RISC based systems was ~$40B in 1997. Last year it was about $20B.
It has been more or less monotonicaly shrinking over these 5 years. Part of this is the effect of the
recession but most of it is due to the competitive effects of Xeon moving into the workstation and low
to mid range server market.
The reality, however, is that there is a multi-billion dollar market for high end solutions.
Yes. HPC alone is ~$5B.
The difference between Itanium and RISC is that Itanium is not proprietary,
Not true - try licensing IPF from Intel to build compatible processors. OTOH, the MIPS, SPARC,
ARM, and PowerPC ISAs have all been licensed to third party processor houses.
I think what you mean to say is that IPF is the first high end processor to target the server
and workstation market with a entirely merchant chip sales business mode - just like x86.
In contrast the high end RISCs are basically the house processors of their respective owners
and thus employ a vertically integrated platform business model.
The development of Itanium infrastructure extends across the industry, making it by the
very definition an "industry standard". Itanium has already demonstrated performance and
price/performance advantages over all other RISC products.
The common platform across multiple vendors factor is highly important. This allows
potential economy of scale and customer choice of vendors that the RISC world, with its
tower of Babel approach, never could achieve.
Power4 still gives Itanium 2 a run for its money, but that will once again change once
Madison launches.
Power4 is definitely the only competition in Madison's class. IBM has the wallet and CPU
and semi know how to keep it competitive for a long time. The problem is Power4 relies
on expensive system level packaging to be competitive. The PPC 970 demonstrates
what happens when this architecture is separated from mainframe class infrastructure.
Also, Power4 is one of the last vertically integrated platforms. Customers lock themselves
into IBM, for better or for worse. It should be good struggle over the next five years.
Chipguy, the architectural weaknesses of x86 have always been in the areas of limited registers
and complex memory management.
You forgot two biggies: 1) complex, sequentially encoded variable length instructions and
addressing modes and 2) CC based comparison and conditional code execution. AMD64
does nothing to address these and in fact the extra prefix byte to address the paltry 8 extra
registers makes (1) worse.
With the AMD64 design we see systems that can scale very efficiently through 4
processors, and good efficiency through 8 processors on a single mobo. With a HT switch,
large many-processor systems are very feasible.
AMD64 has nothing to do with that. You should learn the distinction between an instruction
set architecture and a processor implementation. The system level features of the Opteron
processor you describe are a pale imitation of a very good and ground breaking RISC chip,
the Alpha EV7, which gluelessly scales to 128 processor systems with far better scaling
characteristics.
Every major innovation in uP design since the early 1980s has been done first in a RISC
design - superscalar execution, hardware multithreading, chip level multiprocessing, multi
level on-chip cache, out of order execution etc. That is because x86 architects spend so much
time, money, and effort wresting complexity and legacy ISA semantic alligators they don't have
much strength left to do really original and innovative work. IPF has some complexity issues
of its own compared to streamlined RISC designs like MIPS, ARM, and Alpha but it is still far
better than x86. If it does catch on widely it will free Intel from a lot of the straightjackets
and restrictions that x86 imposes now and hopefully will allow progress in processor design
to regain the pace it had during the golden age of high end RISC (late 80's to late 90's).
x86 has grown quite a bit since EPIC was first invented. I don't think anyone at the time would have believed that current x86 performance was even possible. Given the proper foresight, I think it would
have been better had Intel forced a 64-bit x86 architecture, instead.
I disagree. As good as the implementations are, x86 is a plague
on the industry. If engineers are freed of the working around
its so many limitations and problems we will start to have some
real breakthroughs and innovations. It is no accident that x86
has found little success outside the realm of Wintel PCs and
servers. The x86 ISA has to go and only Intel can replace it.
On the other hand, Intel has proven time and again that they can take a mediocre design and turn it into the best product on the market.
I don't think EPIC/IPF is a mediocre design. It has nearly all
the benefits of RISC while avoiding the worst mistakes of some
RISC ISAs. I would rank it behind the best RISCs and ahead of
the worst RISCs. And all far above x86. The architectural
benefits of IPF over x86 for the FP and DSP intensive nature
of future performance limited apps and man-machine interfaces
is substantial.
chipguy, as I told we have appriximately 15 computers per each person, for various purposes. If we
use $8k workstations, that will be $120,000 of hardware per person, not counting some few really
expensive servers we have.
??????
Perhaps if you just bought one decent workstation for those who need it you wouldn't
need 15 computers per person.
So let me repeat, I do not read Dan3's posts because he is a bald-faced liar.
Hmmm interesting. Apparently calling someone a liar is ok but saying they
engage in hyperbole, obfuscation, and sophistry isn't. I think some people
are in dire need of a dictionary. :-P
Itanium took $5 to $10 Billion to get to where it is today
Since you are making numbers up why not $50 to $100 billion?
Intel appears to have pressured SPEC into
basing much of the total score on art.
Wrong. SPECfp2k score is the geometric mean of 14 subtests. Art
is equally weighted with the other 13.
You are certainly in fine form today. You should include a disclaimor
with these posts - any similarity to actual events or facts is purely
coincidence and not intentional.
Sorry but a microprocessor is a bit more complex than a NAND gate. Assuming
AMD engineers are on the ball in both the bulk and SOI versions the best speedup
that can be expected is 10 to 15%. Given the Opteron results to date, it looks like
AMD engineers aren't yet up to speed (so to speak) in the fine art of SOI circuit
design. Maybe the IBM boys will throw them a few pointers if they ask nicely.
Better look again, Opteron beats Itanium in 10 of 14 SPECfp benchmarks
...
http://www.aceshardware.com/SPECmine/index.jsp?b=3&s=0&v=1&if=0&cf=0&cf=1&cf...
Curious. I tried your link and you seem to have configured SPECmine to ignore all
results from HP and SGI in order to pick up the Unisys score for Itanium under
windows. LOL, I am sure it was an accidental oversight on your part, right Dan3? ;^)
Perhaps you should have a look at the 4-way SPECfp_rate2k score for the SGI Altix
3000 - 58.4 compared to 49.2. In three weeks IPF will ship in 130 nm, just like Opteron,
and then Opteron will be a flyspeck in Itanium 2's rear view mirror. Bye bye flyspeck.
Unless there is a huge suite of Windows-based desktop apps being developed for Itanium (or the
existing suite can be run on Itaniums w/ a minimum of performance impact and cross-platform issues), I
don't think the software issue will be quickly resolved.
Sorry, I guess all my engineering colleagues and I are old school. We don't consider anything
running Windows a workstation almost by definition. The NT workstation wave in the late 1990s
was a disaster for countless reasons so we kept on buying serious machines to do serious
work. In the last few years Linux on x86 has become very credible (even a high end PC beats
the snot out of a SPARC box across the application spectrum) and the CAD ISVs are starting
to respond. Unlike Linux on x86, Linux on IPF can do everything Unix on RISC can do. And
it is still cheaper, dumpster diving aside.
BTW I am suprised, no shocked, by this comment coming from you. I have heard the great
Windows consolidation experiment in engineering/EDA at Intel was quietly ditched years ago.
We use mostly Ultra5's and Ultra10's for desktops. They are around $1,000-$2,000 on secondary
market now.
ROFLMAO!
You are talking about the price of *used* 2 or 3 year old, 350 to 400 MHz US-IIi based
Sun entry level workstations? Those things were jokes when they were brand new. A
decent garage sale PIII celeron would run circles around these POS. What the heck
do your people do with these "workstations"?
So I don't know who is targeted by $1,300 Deerfields, but definitely not real customers.
Real workstation customers need FAR more power than the obsolete junk you are
talking about. And they are willing to pay far more than junk prices to get it. I don't
think I have ever used a workstation in my career that cost less than $8k. Most of
them cost in the $20k range and some went as high as $40k.
Yes, global market share in flash memory. Unfortunately it doesn't
state the measurement period end date or length.
As I told you, my company is oriented toward sub-$2,000 workstations
These are PCs. If it makes you feel good to call them workstations, by all means
do so but that isn't the way HW vendors and market research firms categorize
workstations. Here's a helpful discussion of the difference between PCs and
x86 workstations. Its about 18 months old but useful nevertheless:
http://www.deskeng.com/articles/01/nov/special/main.htm
BTW, how's your company's Yugo "stretch limos" working out?
I didn't read it on line. It was in the latest BW magazine with the cover
story about Samsung. I am sure you can find BW in a convenience
store near you.
As a pro-Intel guy, I worry more and more that in the workstation market, Itanium might be
swimming against the tide here, despite having superior floating-point performance.
I wouldn't worry about that. The current issue holding IPF back is software and that is
quickly being resolved. Workstations are in a tug of war between Xeon and RISC. IPF
provides the FP superiority and 64 bit addressing of RISC but at a price structure much
closer to Xeon. Opteron will provide even lower costs and 64 bit addressing but will
remain far behind IPF in FP performance. And there is a question of OEMs offering
Opteron based workstations in the first place.
The Deerfield model of Madison has workstation written all over it. At a reported price
of $1300 and clock rate of 1.3 GHz it will have power dissipation comparable to a mid
range Pentium 4 while offering FP performance on Linpack and SPECfp2k likely more
than 50% higher than the fastest Opteron. It will make an excellent upgrade for HP's
z2000 and z6000 workstation lines in three weeks.
AMD ramping production on 65 nm parts is a long way off. It has to survive as a viable
business until then. Replacing Athlon with 130 nm A64 does not seem to make sense
unless AMD can raise A64 clock rates beyond Athlon and show a performance delta
(with a 256 KB L2) over Athlon big enough to warrant at least 50% higher ASP.
But it's hard to estimate correctly, I'm not a business person. I just feel that you are cheating somewhere
I thought my back of the envelop argument was highly favourable to AMD. In reality the A64
will displace the highest frequency, highest priced Athlons first. These are priced well above
AMD's $60 ASP and bring in most of its revenue above variable manufacturing costs. As the
A64 replaces them the pricing delta above Athlon will have to be even larger to keep AMD's
overall margin the same.
Do you expect AMD will accept lower margins on A64 than for Athlon? Last I heard Athlon
ASP was around $60. If A64 is initially 50% more expensive to make than Barton then AMD
would need 50% higher ASP initially to keep its margins, such as they are, from dropping
further. That would translate into a $30 higher ASP at the front end of the distribution
channel and the price delta will only grow before it reaches the end user. Will A64 mobos
be >= $30 cheaper to compensate? Given the years that Athlon mobos have been in the
channel I'd would predict A64 motherboards would be more expensive, not cheaper.
There is no getting around it - the A64 will be more expensive than Athlon. If AMD can't
convince buyers that it offers a proportionate benefit over Athlon then it will have a
very problematic product transition on its hands.
LOL, nice find. Thanks for clearing that up.
Face it Chip, you agree with anything Intel does and says. You have your, umm principles,
yeah thats the ticket.
Wrong. I call'em as I sees'em.
I think Intel was completely wrong and pig-headed trying to drive Rambus into the mainstream. They
wasted at least a billion of dollars of share holder money in direct subsidies to companies like Micron
to encourage the transition. AFAIK the number of RDRAM parts sold by Micron is precisely zero. Then
there was the 820 three slot motherboard recall debacle. And Intel obviously has work to do with test
coverage assessment procedures prior to release to manufacturing given the McKinley and PIII/1.133
problems. And it took Transmeta to convince Intel that the mobile computer market deserved better
than hand-me-down desktop chips.
I don't agree with everything Intel says and does and will freely point out missteps past, present, and
future. Too bad there are some ideologically driven partisans here who aren't intellectually honest
enough to do the same for AMD. Are you one of them?
But low speed DFT can't test CDR and signalling functionality at full speed. Perhaps AMD splits
Hammer family part testing across two classes of testers, their current units for functional and
parametrics, and a specialized high speed, mixed signal unit for HT link operation. Testing in
that order would also reduce the capacity needed for the new tester since it would weed out all
devices failing for all causes not related to the HT links from the feed to the new tester.
An alternative approach to testing the HT links would be to build custom high speed test logic
on a specialized DUT card and have a conventional tester drive and interrogate this logic using
extra test channel capacity. The engineering time and effort to do this might not be cost effective
for Opteron (compared to buying a specialized tester) but perhaps it would be for A64. Again,
another possible true cause of delay for A64.
Good point. It is like Intel selling Coppermines to Microsoft for Xboxs on effectively
a cost plus basis. Stopping further Athlon development and selling it on a cost
plus basis to the global ultra low cost PC market might make sense. The problem
is that it means splitting up AMD fab capacity between SOI and bulk runs.
Regardless, I think Athlon will live on for much longer than many people think.
Are you saying that AMD will ship Hammer family parts without fully testing the HT links?
Sorry, but I doubt any semico would do that. Obviously they wouldn't need much new
tester capacity for Opteron given its volumes. Perhaps a reluctance to shell out for
much higher new test capacity for A64 was a factor in delaying it. I remember that the
issue of needing new testers was a major reason that DRAMurai opposed Rambus
so strongly.
chipguy, why do you think A64 is more expensive to make than Barton? The amount of good dices per
vafer will be comparable, packaging comparable. Ok, let it be even 20% more expensive (I think it won't
be) - so what? Even 10% of sales increase will compensate 20% of cost rise.
Consider a 256 KB A64. It will be slightly larger in die size, it will have a smaller fraction of
die area protected by repairable redundant structures. And it uses SOI processing. The
package it goes into has more than 50% higher pin count. The high speed HT links will
increase testing costs. Finally, A64 is at the top of the learning curve while Barton is at
the bottom. I wouldn't be surprised if a 256 KB A64 cost as much as 50% more to make
than Barton in the first few quarters of full scale production. I doubt it would ever drop
below a 30% premium.
I really think AMD has painted themselves into a corner with A64 and SOI. For their sake I
hope they can pull A64 clock rates above 2.2 GHz with good yield or they are going to be
in a world of poop in the desktop market.
With costs down and a complete line of products, AMD will be able to pick the area(s) where profit avail:
Brave words my son. AMD hasn't been able to pick profitable areas for many,
many quarters now.
ATHLON BARTMAN DESKTOP-this has been bread and butter
More like a thin gruel. Competitive pressure is so great that AMD has gone
Cyrix on the QuackHertz of its high end. Even true believers see through the
BS. ASPs stay in the basement.
OPTERON, server, workstation and enthusiast-another great product
Nice product, shame about the (lack of) OEMs. Let's see if AMD can build a
business around selling to a handful of partisan trust fund gamers.
NOTEBOOK, SFF will keep things interesting-Keeps Intc honest
LOL, Banias is a category killer. AMD will get the floor sweepings as usual.
FLASH, FASL is seperate from AMD -Mirror Bit, kudo's AMD
Competing on price is great, but only if you can make money at it. This is
a wait and see.
A-64, Out for Christmas?-Windows64 would be frosting on the cake, wait and see, no problem
Great, replace Barton with a device that performs worse yet costs way more to
make. I think AMD will find an excuse for another slip. SARS seems to be the
hip excuse these days. Maybe Hector will copy his old friends at Motorola.
ALCHEMY, pretty quiet, that market has potential
Sorry, but ARM and MIPS has stratified the embedded control market with ARM
taking the low cost, low power, mobile segment. A low cost, low power MIPS chip
is a queer duck still looking for an application.
Incremental gains going forward from a quite a way back. All aboard.
Like 46% product margin in 2000, 33% in 2001, and 22% in 2002? Can't get
enough of gains like that!
Doesn't look like too bad a loss. According to IC Insights here's how
the global flash market share for the top 4 players breaks down:
Intel 27%
Samsung 14%
Toshiba 11%
AMD 10%
Very interesting numers you post. Do you know how many Xeons are seling each year?
Not specifically. FWIW the world sales of all servers was about 4.5m (systems not chips) last year.
The Xeon had about 87% share, by system units or 3.9m. If you estimate that the sales volumes are
heavily weighted to dual processor systems and add to that Xeon sales for workstations and we
are probably talking about processor numbers on the order of 10m per year, maybe more.
Keep in mind that the ~10% of servers that use RISC processors have higher system value
than the rest of the server market combined. That is why Intel created IPF - to crash the RISC
country club. BTW, the value of Intel (Xeon + IPF) based servers will likely exceed that of RISC
based systems this year for the first time.
Do you have any link where someone assembles this info year-by-year?
Recent data is hard to come by because the market research companies charge big bucks for
their reports. Keep an eye out for companies and news agencies that disclose portions of recent
IDC, Dataquest, MDR/in-stat, etc reports to spin press releases and news stories.
But still, why do I have to pay from 40 to 70 K for that server?
That's a function of the market it addresses. It is competing against IBM pseries 630,
SGI Origin 3200 and Altix 3000, and Sun Fire 880. I doubt the 5670 pricing is out of line
compared to those systems. HP probably doesn't want to undercut its own RISC based
mid range systems by too much either.
Anyway, I am a great believer in Adam Smith's "invisible hand" of capitalism. If HP is
charging too much then they will have to lower their price or not sell as many as they
want.
I don't pay much attention to predictions of sales except for relatively mature products in
stable market segments. Any number of factors can make huge differences either way.
I'd rather see some hard in-the-bag sales numbers from Intel and its OEM partners.
However, *if* MDR's estimate is in the ballpark it would be quite an accomplishment for
a new architecture in the current business capital spending environment. The 200k/yr
figure nearly doubles the peak sales of Alpha processors, and approaches the peak of
HPPA processor sales. IIRC the maximum number of SPARC processors Sun ever
shipped in a year was around 550k. BTW, I think AMD will be hard pressed to sell 200k
Opterons this year, even with bargain basement pricing.
There is no L4 cache in the rx5670 - check the SPEC submission. Learn to count,
the L1s are primary, the L2 is secondary, the L3 is tertiary. IMO the term massive
referring to 3 MB of on-chip cache in a 180 nm microprocessor is accurate.
NA libraries seem to scale well on Opteron
4 CPU : 12,130MFlops (N = 30000, NB = 112) ... 84.2% of peak
Not bad, for an x86. Too bad it takes 130 nm feature size, SOI Processing,
and nine levels of copper interconnect to get there.
http://h21007.www2.hp.com/dspp/files/unprotected/itanium_momentum.ppt
4 CPU HP rx5670 15,127 MFLOP/s, 95% of peak
Too bad about that shared bus architecture eh?, LOL. When IPF joins Opteron
at 130 nm feature size next month expect 4 CPU system Linpack scores of over
20,000 MFLOP/s.
Like Intel's previous iapx432 resurrection attempt, the 860, I expect that Itanium's
only success will be in embedded applications such as printer and raid controllers.
Intel learned a lot from the i860 debacle. The i860 had virtually no OEM support, while
IPF has virtually all OEM's support. The i860's unique performance features couldn't be
accessed through high level programming languages while, there are a several excellent
compilers for IPF that make almost full use of its major features. The i860 had little
software support and no seeding of development systems among ISVs. Intel has spent
years seeding thousands of IPF development systems among ISVs as well as providing
hundreds of millions of dollars of funding for porting and this effort is starting to show
significant results.
Nice to see that we agree on something, for once.
That you are an intellectually dishonest and disingenous person with an apparent reading
disability? Sure, I'll agree with that.
The question is, did Intel make x86 big, or did x86 make Intel big. I think (gross
oversimplification coming up) it was the latter, which makes Intel's decision to
abandon x86 look like a big mistake.
Who says Intel is abandoning x86? They have multiple new generations of x86
processor cores in development. The two product lines will overlap for many
years (three product lines actually, don't forget about Xscale).
Of course, if it was the former, then they can make IA64 just as big as they made x86.
Intel's strategy seems to be to let the HPC and server market adopt IPF processors
for its performance on commercial and FP intensive applications. In the years ahead
when 64 bits become useful or even necessary for power user's desktop applications
IPF uPs will be in 90 nm or better and Intel can produce moderate cost and power
models attractive for desktop or even laptop PCs. Less demanding users will still
buy x86 processors.
In AMD hands the Opteron chip is a very interesting product, which can take 10% of the server market.
That is not totally unreasonable (by units, not by processor revenue or system revenue). But
only if AMD can sort their SOI issues out and get a major OEM on board within the next 3 months.
After that it won't be able to shake its image as flash in the pan time passed by.
In IBM hands Opteron may be a weapon, which will kill both Xeon and Itanium with quick and painless
death.
Just like PowerPC killed off x86 right? :-P
In the huge clumsy hands of IBM the Opteron would end up like their "blue lightning" processor.
Btw, now is the first time in the whole AMD history when they have a chip, which is
consistently selling for above $500.
That remains to be seen. There has historically been a large gap between the
list price for AMD processors and the price that it actually sells them for. Given
the state of Athlon sales it should be readily apparent in their next quarterly
statements if Opteron is contributing materially to either revenue or towards
raising AMD's ASP.
So, IPF can't dominate the market by definition, as it will never be price/performance competitive with IA32.
Why do you think this?
Please tell - do you beleive in $50 Itanium-compatible chip? If yes than when?
Going by the trend of RISC processors, before 2010. The MIPS R2000 appeared
in 1986 as a $2000+ server chip. A decade later you could get an improved version
of that design from IDT for embedded control applications for under $10. Now the
same core is a few mm2 - Sony threw it onto one of the PS2 ASICs like a minor
peripheral to run legacy games. Ain't Moore's Law great!
I was talking about 64now!, not 3Dnow!
As in the case of SIMD, the Intel standard for 64 bit computing will dominate the Industry. The
problem for AMD is the barrier to imitation will be much higher than it was for SSE and SSE2.
chipguy, so your memory tells you that 3Dnow! was receiving warm industry reaction,
High fives and butt patting among the true believers and enthusiasts is hardly "warm industry
reaction". Getting public committment from major OEMs like HP, IBM, Dell, SGI, Bull, Fujitsu,
NCR, Unisys etc, is.
Microsoft was rushing to support it
LOL. If I ever have a heart attack I hope I am not "rushed" to a hospital in a similar manner.
IBM was rushing to manufacture it
IBM will rush to manufacture for any company with the green. For example, they also manufacture
HPPA and Alpha processors, two potent competitors to their POWER processors so a manufacturing
relationship with IBM Micro as a sign of general corporate support is laughable. IBM's committment
to AMD is as deep and meaningful as a hooker's is for a guy with a full wallet.
it was superiour to competition?
That is highly debatable. Regardless, the trashbin of computing history is full of former competitors to
Intel's chips that were technically superior in some or many ways. That will never be enough on its own.
Are you broke yet?
Not at all. You should really be asking that of AMD at every quarterly CC and mid quarter update.