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Tench -
I doubt the memory request is speculatively issued on every access to L2. That would create way too many bus requests that would later need to be cancelled, especially when you're talking about L2 hit rates of 95%.
So how do the other processors snoop the address otherwise?
sgolds -
Just as comparing clock rates has become complex now that we have so many divergent architectures (Athlon, Hammer, Centrino, P4, Itanium), it is getting very hard to compare die size as different architectures combine different functions on the same die.
You have a point but I think you missed the original one. The issue was why is Opteron's die so large compared to Athlon, and additionally why is it slower? Had AMD done Opteron on bulk silicon it would have almost certainly been faster and maybe smaller.
Paul -
Intel uses a traditional L2 cache as follows: First the processor checks L1 cache, if it isn't there then it checks L2 cache. If it finds it there then a copy is made into L1 cache and then into the processor register (or to another cache location, if it is a memory to memory move). If it doesn't find the item in L2 cache then it gets it from main memory, into L2 cache, into L1 cache, etc.
Some others can address this better than I but I think it does all of those operations simultaniousley. If it's in L1 it cancles the L2 and main memory request. If it's in L2 it cancles the memory request. No need to wait while it's checking each in sequence.
sgolds -
Am I the only one here old enough to remember 8086 segments and offsets allowing 16bit registers to address 20 bits? Or in the case of the 286 they could address 24 bits.
Sounds like a revisit to me and Intel already does 36bits so 4 more isn't so strange.
WBMW -
Re: SAP scores:
The first entry is a 4-way Xeon DP at 2.4GHGz with 512K L2. I thought the DP was 2-way only?
Subzero -
"Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said
This doesn't speak to the 1 meg L2 or the memory controller or the aHT ports, but the .13u process should have bought back some of the gain, if not all.
Smooth -
If IBM can't, who can? Isn't that, by definition, the limit to which you could produce it.
Ahhhh that's the point.
I can't think of anyone better.
Just what do we really know about IBM's ability to produce volume SOI?.
This is truly a strategic move by AMD. One only wonders about the price. If $45M is the only fee, it's a lot less than a new fab.
IBM isn't know for cheap fab contracting. They're going to want their cut.
Paul -
Add that factor to the integrated memory controller & aHT circuitry and its size looks a lot more reasonable.
It makes it a lot more understandable but from a manufacturing standpoint it's no less unreasonable.
Intel's Otellini Claims Wintel No. 1 In Benchmark Battle
By Steven Burke, CRN
San Francisco
6:31 PM EST Thurs., Apr. 24, 2003
Let the benchmark wars begin.
Intel President and COO Paul Otellini on Thursday claimed the Wintel partnership now has the world's No. 1 single-system TPC-C industry-standard benchmark in the battle with high-end Unix midrange and mainframe systems.
Speaking at the Windows 2003 product launch here, Otellini touted the record-breaking benchmark performance of a Hewlett-Packard Superdome server based on Intel's forthcoming Itanium 2 processor, code-named Madison, and running Windows Server 2003 and SQL Server 2000 Enterprise Edition (64-bit).
"This is absolutely the fastest transaction [system] on the planet," boasted Otellini, drawing large cheers from several thousand Microsoft partners and industry executives gathered for the product launch. "Intel and Microsoft know that being No. 1 is a good place to be, but we know we must fight to stay there."
Intel, Microsoft and HP claim a benchmark result of 658,277 transactions per minute (tpmC), exceeding the performance record set by a 128-processor SPARC-based system from Fujitsu. The benchmark, which moved Intel up from the No. 5 performance position last year, was achieved on a nonclustered, 64-processor HP Superdome server.
The HP benchmark, which was achieved on Thursday morning, outperformed an NEC system, which had brought Wintel to the No. 2 position in a benchmarked test only last week.
Otellini said Itanium is gaining momentum with new OEM wins. He claimed the number of Intel OEMs building Itanium two- and four-way systems will double to 40 this year, up from 20 in 2002. He expects 80 OEMs to be building two- and four-way Itanium systems by the end of 2005.
Otellini said the number of OEMs building systems with eight or more processors will double to 10 by the end of this year, up from five in 2002. He predicted more than 15 OEMs will be building eight-way and above Itanium systems by the end of 2005.
Microsoft CEO Steve Ballmer said the performance benchmark "blows my mind." Ballmer recalled trying to lure legendary operating system developer and current Microsoft developer Dave Cutler to the company. Early on, Cutler had told Ballmer he did not want to work at a "toy operating system company."
With the HP benchmark, Ballmer said he could now look Cutler in the eye and proclaim Microsoft is no longer a toy operating system company. "We have the highest-performance operating system in the world," he said.
Ballmer also announced what he called the No. 1 performance benchmark in the world for a single-system Siebel Systems CRM application implementation, supporting 30,000 concurrent users on an Itanium-based Unisys system.
"That's an amazing thing if you go back four, five and 10 years ago when some were questioning [whether] PCs [would] be able to run the biggest jobs. Now we have the No. 1 benchmark of any platform in the market," he said.
Dell demos Itanium 2 server
Company reveals few details about new system
By Tom Krazit April 24, 2003
Dell Computer publicly demonstrated an Itanium 2 server for the first time at Microsoft's Windows Server 2003 launch event in San Francisco Thursday, and said it will release such a system later this year.
Dell has expressed support for Intel's Itanium 2 processor in the past, but has been reluctant to share details about its plans for the chip. Thursday's demonstration didn't mark a change in that strategy, as Dell spokesman Bruce Anderson declined to comment about the server's price, configuration, or specific launch date.
It was also unclear whether Dell is waiting for Madison , the next version of the Itanium 2, to launch in the middle of this year before it releases a system using a chip from the Itanium processor family. Anderson also declined to comment on whether the performance benefits expected from Madison 's higher clock speed and larger cache were the reason for Dell's year-long hesitation in deploying an Itanium 2 server.
Itanium 2 is a 64-bit processor launched last July that uses an entirely different instruction set than 64-bit RISC (reduced instruction set computing) processors or 32-bit processors from Intel and Advanced Micro Devices. It was developed in conjunction with Hewlett-Packard, which has been the primary backer of Itanium 2. The chip has won praise for its performance, but it requires IT managers to recompile all of their applications for the new instruction set to take advantage of that performance.
Dell and IBM have been reluctant to release servers using the chip. IBM announced this week it would release a server using a competing 64-bit chip, AMD's Opteron.
Dell, based in Round Rock, Texas , expects to sell Itanium 2-based servers to the high-performance computing market, Anderson said. Intel released benchmarks Thursday claiming an HP server with 64 Madison processors, Windows Server 2003 and Microsoft's new 64-bit SQL Server database achieved the highest-ever single-system transaction processing score as measured by the TPC-C benchmark for high-performance online transaction-processing computers. However, benchmarking claims are notoriously unreliable, according to one analyst.
"In general we don't tend to pay a lot of attention to benchmarks. They show a vendor's dedication to a particular area, but we advise our clients to look at actually running a database within their own application environment. Is the database going to support their applications? Is the packaged application available? Those are the sort of questions they should ask," said Betsy Burton, an analyst at Stamford, Conn.-based Gartner.
Joe -
I think some of these unknowns will be answered in next 2-3 months, when Opteron makes it to workstations, and can be put through paces by benchmarkers and overclockers. Also, in this time frame, if there is a new speed grade, it would indicate that things are on the right path, if there is none, it would be a warning flag.
I agree. We shall see.
Now tell me, was this a vapor launch?
wbmw -
I don't think you'll see many tier-1 OEMs jumping at the opportunity to build a system on a brand new architecture just to have equal performance to Xeon, lower performance than Itanium 2, and equal price/performance for each.
Equal to a Xeon? That's not what I read from the benchmarks, unless Intel is about to release a significant upgrade to their current offerings.
Joe -
Obvoiusly AMD will use Dresden before outside foundry. But AMD can sell more than Dresden can make, IBM foundry deal would be a way to increase production. It'ssomething very hypothetical, since it has been probably 3 years since the last time AMD was capacity constrained.
Although we are all impressed by the excellent benchmarks Opteron posts, there are still many unknowns. Can AMD produce it and if not, what makes you so sure IBM can?
wbmw -
Thanks for the encouraging news. In addition to the staggering 64 processor score Madison beats Opteron by nearly 50% in 4-way systems! Of course someone will point out the $tpcc but that's another argument.
EP
sgolds -
Didn't the deal include jointly building a 65nm 300mm factory? Not hard to do a little joint manufacturing with that start, is it?
I could be wrong but I remember the deal only involved joint development, not a new fab.
Are you saying that Madison is released?
wbmw -
Awesome scores!
They say the 32-way system will be available in Oct. The 8-16way can be ordered today. Any idea when those will be available?
Economaniac -
now you are just encouraging elmer.
I've given people here the tools it figure it out themselves.
And this is the thanks I get.... :)
Intel plans Itanium course correction
By Stephen Shankland
CNET News.com
April 23, 2003, 4:24 AM PT
Intel will release software later this year designed to dramatically improve how well its Itanium chips run programs written for its Pentium or Xeon processors, CNET News.com has learned.
The move is meant to address a weakness that hampered the adoption of high-end, Itanium-based systems.
Itanium chips currently include circuitry that lets them run the 32-bit software of "IA-32" processors such as Xeon or Pentium. But that circuitry's performance has been so poor that not even Intel advocates its use.
The new software approach, called the IA-32 Execution Layer and code-named btrans, will give the forthcoming 1.5GHz Itanium 2 the ability to run 32-bit software about as fast as a 1.5GHz Xeon MP, Intel spokeswoman Barbara Grimes confirmed.
The software could make Itanium processors more appealing to customers that have been reluctant to use Itanium systems because of the difficulty of running older 32-bit software, analysts said. In addition, Intel's new strategy could undermine one of the key advantages of the Opteron processor AMD introduced Tuesday because it allows customers to gradually transition to new applications without having to discard their current applications.
AMD's Opteron is designed to run 32-bit code as fast as possible, meaning current applications don't need to be replaced. Itanium, on the other hand, emphasizes 64-bit software with the ability to run older 32-bit software as only a second priority. With both Opteron and Itanium, the software must be rebuilt if it is to take advantage of the 64-bit features, such as the ability to address large amounts of memory.
"A customer who likes Itanium but also has 32-bit workloads they can't move immediately to Itanium is really in a quandary. AMD's claim to fame is that you can run that 32-bit software till the cows come home and have 64 bits, too," said Insight 64 analyst Nathan Brookwood. However, Intel's software emulation technology "does blunt AMD's story a bit," he said.
The emulation software's speed, if it meets Intel's expectations, wouldn't be far behind the top 2GHz speed of today's Xeon MP, a chip that like Itanium is designed for multiprocessor servers. It would lag more substantially behind the speed of 3.06GHz Xeons for dual-processor computers, though.
Still, it would be vastly better than the current technology for executing software for IA-32, also called x86 after earlier Intel processors such as the 386 and 486.
"They said Itanium would never be their fastest 32-bit processor, but it would be in the ballpark. The original x86 hardware execution mechanism wasn't in the ballpark. It was barely in the parking lot around the ballpark," Brookwood said.
The emulation move is also likely to be more palatable to customers than "Yamhill," an Intel project that sources have said is similar to AMD's 64-bit extensions to Intel's 32-bit design rather than the dramatic departure Itanium represents. "This could be another way to respond to AMD without necessarily compromising their Itanium strategy," Brookwood said.
There are risks, though. Emulating one chip on another has historically been difficult and is most often used as a crutch during migrations, such as when Digital Equipment switched from VAX microprocessors to the Alpha. Apple managed the feat when it moved its computers from Motorola's 68000 line of processors to its PowerPC line, but could do so only because the new chip represented such a performance bump that it could offset some of the performance hit caused by running an emulator.
Intel's Execution Layer software is a module that plugs into an operating system and emulates the IA-32 processor, Grimes said. Intel is working with Microsoft and Linux sellers on having the software included in their operating systems.
Microsoft and top Linux seller Red Hat didn't immediately respond to requests for comment. SuSE declined to comment, but a source at the company said the second-largest Linux seller is working to support the technology.
"We are working with Microsoft, with the Linux (project) maintainers and Linux operating system distributors to ensure the Execution Layer is functional and ready for quick, broad deployment when it's validated," Grimes said.
The Itanium effort
Itanium is an ambitious attempt to create a chip architecture that will last for more than a decade. Hewlett-Packard initiated the project in 1988 then signed a partnership with Intel to design and manufacture the chip in an effort to spread the processor as widely as Pentium instead of seeing it consigned to the small niche many high-end processors occupy.
But the Itanium family arrived years later than expected, in the midst of an industry spending freeze, and the family's first member, code-named Merced, was largely a dud.
Although the second-generation Itanium solved performance problems, it didn't change the larger problem: that software has to be rebuilt to take advantage of the chip's abilities. And because the anemic 32-bit performance made it hard to run older software, Intel rivals such as AMD and Sun Microsystems were able to exploit the fact that their new chips don't force customers to deal with a "binary break" that makes older software useless.
And that led Intel to consider emulation technology.
"If Intel could find a way to have IA-32 code run reliably and relatively quickly on an Itanium processor, it could only help its adoption," said Illuminata analyst Gordon Haff.
HP, the company with the biggest stake in the success of Itanium--because it's moving its entire server line to the chip family--is supportive of the move.
"We're pleased with any technology that will boost the performance of Itanium-based systems for our customers. We expect this (IA-32 Execution Layer) to help customers as they migrate their applications from 32-bit to 64-bit on Windows and Linux," said Brian Cox, worldwide product line manager for HP Business Critical Systems.
Intel will keep the hardware-based IA-32 support at least through the Itanium II 9M model due to arrive in 2004, Grimes said. She declined to say whether the company would rely solely on the Execution Layer software after that, but analysts believe that move is likely.
Removing the hardware component likely would liberate Itanium from design compromises the chip needed to accommodate the 32-bit code, Brookwood said. And Mercury Research analyst Dean McCarron noted that "getting rid of the hardware piece of it means fewer transistors, smaller die size, and (that Itanium would be) more manufacturable."
Grimes, however, said removing the hardware support wouldn't change the processor size significantly.
Several factors will determine the future of the emulation layer. On one hand, Intel engineers could improve the software in succeeding generations, and its performance will increase as newer, faster Itanium models debut. On the other hand, Intel has been aggressively boosting the speeds of its 32-bit chips.
One advantage of the emulation software is that it can be more easily adapted to execute IA-32 instructions that older IA-32 chips lacked. For example, the existing Itanium circuitry can't execute the SSE instructions that have been boosting some mathematical operations since the days of Pentium III, much less the SSE2 follow-on in Pentium 4 and whatever might come later.
The new layer doesn't change Intel's overall Itanium strategy of encouraging computing companies to rebuild their software for Itanium, Grimes said. Customers needing top 32-bit software performance should still buy Xeon systems, she said.
"Itanium is first and foremost designed to run 64-bit," Grimes said. "The 32-bit support is in there as a migration path for people as they get over to 64-bit, or for nonperformance (critical) applications they might not want to migrate."
Economaniac -
As time is a commodity that can be traded as easily as shares or options in exchange for cash or equity, we should mention the notion of rolling. Should someone sell a $10 June call and should the share price be in excess of $10 approaching expiration, one does not have to lose their shares. Time has value and can be used to purchase more equity. A June $10 call that is in the money and approaching expiration has intrinsic value but the time value has evaporated. It could be bought back and a new call for a later month could be sold for a net profit because the new call has time value that the old one lost. It is also sometimes possible to roll up, meaning that the price of a June $10 call may be equal to that of a Jan'04 $12.50. The time difference buys equity. It is hard to do this on a stock with large relative strike price increments like AMD but QQQs are extremely good because the increments are $1. I roll up and out my QQQs every time I can go out 2 months, raise the strike price $1 and pocket $0.50.
The point is you don't necessarily have to lose your shares.
wbmw -
I wrote some June $10s today and got $0.30.
YB -
I pay a plat fee plus a fixed amount per contract. The more contracts the cheaper it is per contract. You really need to be selling a few contracts to make it worthwhile but you don't have to be an institution. Many people like me sell in the 10s or 100s or more of contracts and the cost becomes quite low. My cost is typically 1.5 cents per share. I use Schwab. If anyone knows of a better rate I'd like to know about it.
YB -
As individual investors can't write $0.15 calls with big broker comission, all those are institutions
I do it all the time and despite appearances I'm not an institution.
Chipguy -
There are a lot of issues and it would honestly take far too much time to even scratch the surface. And it would probably bore most of the people here to tears.
Not me :)
Spokeshave -
Additionally SOI has better high temperature characteristics than bulk silicon. There *should* be a decided advantage to SOI, and all else being equal, a SOI device should clock higher on lower voltage.
Yes it should, so why doesn't it?
Not a Processor issue at all?
http://www.theinquirer.net/?article=9100
Intel 3GHz/Canterwood BIOS download available in a week
And contact third parties if you need to
By Mike Magee: Tuesday 22 April 2003, 23:28
THE ENGINEERS AT Intel have indeed fixed the anomaly/bug in the 3GHz/Canterwood combo, as we reported yesterday, rewriting a Wall Street Journal story.
But the download won't be available on the Intel site for a week or so, the firm confirmed to us just now.
Readers had complained that when they called Intel support asking for the fix, they were told the fix didn't exist. But that's not true.
Intel will ship the BIOS update with all new shipments of the combo, but people using third party motherboards or machines should contact those people for the fix.
Further, said Dr Chuck Mulloy, a senior Intel representative, the problem with the Intel mobo only applies to the D875PBZ motherboard.
Not a Short
I'm going to define some terms:
#1 A bug is a design mistake where the design says 2+2=3. All devices are affected.
#2 A hard defect is where a defect causes an isolated device to say 2+2=3 because of a shorted line, particle or some such defect caused by the manufacturing process. Only isolated devices are affected and the effect is unique to that device. It will always say 2+2=3 regardless of voltage or temp.
#3 A soft defect is where the effect is only seen on boundry conditions. Normally 2+2=4 but with voltage, temperature or process extremes a device may say 2+2=3, but under less stressful conditions it will say 2+2=4. The anomoly could be a previously undiscovered speedpath that is only now coming into play because of the new bus/core rations or it could be a soft manufacturing defect that slows down a path but doesn't corrupt the data except for making it late, meaning it still works if you slow it down.
#1 requires a design fix, microcode patch or software workaround to fix.
#2 should be easily screened by the test program's basic fault coverage.
#3 should also be screened by the test program but the exact sequence of events that triggers the fault is much harder to find, indentify and screen for. There are more speed paths then can possibly be tested under normal production conditions.
If not a soft defect a design fix could address this but only to the extent where the normal speed distribution is less sensitive and binsplits can be improved.
To me it looked very much like the problem fell into category #3 as the problem was only seen at the last minute and then only in a few units and only under boundry conditions. A perfect time for a new test screen.
Now that Intel has done a software patch it blows my whole theory...
Spokeshave -
Jump right in here, Elmer if you have any opinions about the manufacturability of Hammer. I am not sure what your position is.
Well if you insist....
As I said, I am not a process expert but my understanding is that SOI's main advantage is lowering leakage to the substrate. As chipguy said, there are other mechanisms for leakage as well. When optimizing for performance modern transistors do not fully shut off and leak constantly. This is called sub threshold leakage and is quite large. Does SOI address this? I don't know but I would guess not.
As for Opteron manufacturability, we'll have to wait and see. Yield is the big criticism for SOI and the reason the mainstream avoids it. Too expensive. As economaniac points out, AMD doesn't need high yields to benefit from the very high ASPs Opteron can bring. If AMD can produce this device they have a very good chance of turning things around. I am impressed.
Such a large die on such a temperamental process... AMD keeps life interesting don't they?
ALi picks up 800MHz bus license from Intel
By Mike Clendenin
EET
(04/22/2003 4:02 PM EST)
TAIPEI -- Ali Corp. confirmed Tuesday that it has obtained an 800MHz front-side bus license from Intel Corp., making it the final third-party chipset maker to join in the market.
In the last month, Intel also granted licenses to Silicon Integrated Systems and Via Technologies, the latter of which settled a long-running court battle with Intel over intellectual property.
Ali is set to release samples of a single channel DDR400 chipset in the second quarter. SiS will start volume production of their 800MHz-compatible chips in about a week and Via is already in production of its PT400, supporting single-channel DDR400.
Chipguy -
I'm no device physicist or process guru. Wouldn't the SOI benefits be most pronounced under static conditions? As frequency goes up don't the benefits go down?
Ten -
If it only effects a small percentage of units and only under boundry conditions it can not be a bug. If it were then we would say that every 2.8GHz P4 is a 3.06GHz P4 with a bug.
No?
edgar -
The Opteron is up to 38% faster than the Dual Xeon
Yes it is no some important benchmarks but the reverse is true on some others.
I find it quite surprising that Intel issued a software patch. They said it was seen only in a few units and only under high stress in the lab. This means they should have been able to easily screen this at test. Maybe it saved them a recall from the distributors?
Neye -
the fact that the A64 will have 1/4 the cache and 1/2 the bandwidth of the chip in the benchmarks today
At 193mm2 Opteron is very large and a 1/4 cache A64 won't compete well on the desktop. Although I am forced to admit that Opteron looks extremely good in 2/4 way servers there is a hole in the desktop roadmap. A larger cache A64 is going to be too expensive to make.
it's going to be a tough road for the A64 to hoe.
Actually it's "row to hoe" for the non farm types <G>.
Joe -
What about availability?
Anyone heard anything about power specs?
YB -
Java webserver is running on Opteron 30%-37% faster than on Xeon. We are talking about almost a million of servers here, or something like that.
You might want to look at the other benchmarks before you get too excited.
Bonefish -
What benchmarks are used to test 4 way?
Go to AMD's website. They've got benchmarks there.
Not a Short
You really expect past benchmarks of unpatched systems to match the performance of the new part running the patch?
Yes I expect it. I may turn out to be wrong but I expect it.<G>
I want to say congrats to AMD for producing such an impressive chip in the 2-4 way server space. If they can deliver this it is a real killer. I underestimated it's capability in this area. Workstations are going to be more of a challenge though where I am not seeing nearly as strong a capability.
Now, can AMD deliver?
EP