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Not a Short - You are correct so a quick definition of terms:
Yield = total functional/total possible.
Binsplit = % of Yield that tests to a given speed.
Example: (made up numbers)
P4 Binsplit:
3.40GHz 5%
3.20GHz 15%
3.06GHz 45%
2.80GHz 95%
2.60GHz 100%
2.40GHz 100%
etc.
YB - So your definition of "cherry picking" is slowly building inventory before introduction? I didn't know that. I've heard the term used on boards and was curious as to what you meant by it. So a speed grade that doesn't need to be stockpiled isn't "cherry picked" by your definition?
YB - So, last 2 Ghz parts are not cherry-picked
So can you explain to me what "cherry-picked" means and what is a part that isn't "cherry-picked"?
Petz - Seemed like maybe Intel had grabbed him last time we heard from him.
As I recall, Intel didn't quite have the same high opinion that he had for himself and declined to make him an offer...
Buggi - An interesting observation. The Microcode and Copyright dates of Opteron say 2001. The says to me that Opteron first taped out in 2001.
wbmw - Sold GTW, Made 49%
Good one!
SZ - Any thoughts?
Sorry SZ but I'm not very good at analyzing this. There are lots of others here who are much better than I on this subject.
tek-prophet - I suppose the other option would be to continue to fab the chips on which ever line they are currently being produced (TSMC I think) and report the fabrication costs as COGS. This is, in fact, what National Semi was doing. If you look at the unit profitability and adjusted it by removing amortization and depreciation expenses and by lowering labor cost by 30% (65 laid off, 150 hired by AMD) would it be profitable? Again, we can't know until the quarterly conference call, but I submit that AMD is rational and therefore would not enter into a dilutive transaction -- especially if they have to raise money next year.
The speculation here was that AMD picked it up to use some of their underutilized fab capacity. Can't do that by contracting it out. Once again AMD would be sharing their revenue with a foundry. As for reduction in headcount lowering costs, NSM could have done that too but didn't, why? I'm as puzzled as you are.
tek_prophet - EP, by development costs I meant IP development costs, but you are correct that there will be costs to introduce the chips to the fab. You tell me how much you think that will be -- I have not previously costed an intro. Is it mostly labor? Will that labor be incremental?
You got the wrong guy here for estimating costs. It will take a design team, layout people, a Product Engineering/Test Engineering team and Q&R people. Maybe those are the people they hired? Assuming the Design database is in a synthesizeable form (VHDL/Veriolg) then it's a standard new product development from there out. If it's not synthesizeable then I don't know how it's done.
tek_prophet - Why is there no development cost? If the product is going to be fabed in AMD's fab then who is going to do the conversion, validation and qualification?
Windsock - Proof that IBM's and AMD's SOI process is in deep trouble.
"In a conference call, IBM's chief financial officer, John R. Joyce, blamed a portion of the loss on low yields during the rampup phase of IBM's 300mm fab"..."Joyce said he expected yields to rise, and demand to rebound, in the latter half of the fiscal year."
The failure of SOI makes Intel look smarter and smarter for using bulk silicon to get "only" 3.2 GHz on its 130 nm process.
Intel may still have more speedgrades left in their 130nm process...
wbmw - You also can't get away with claiming zero R&D for these products, unless you expect AMD to invest zero into Geode's future.
That design isn't going to run on an AMD process without all the development work from synthesis onwards. Process conversions aren't fun and they aren't cheap.
wbmw - Most companies that lose more than $4.00 EPS in the last year do not go on spending sprees
Maybe they paid with shares(AMD)?
wbmw - I'm thinking seriously about buying some HPQ. Things look really bright for them.
sgolds - In order to get significant reduction from 100W, does this sound like a simple stepping to you?
No it's not likely to be a simple stepping like just the metal layers. Remember Intel has no significant volume yet on 90nm so they don't have much process history. In the past a company would move an existing product to the new process first so they can separate a design problem from a process problem. Prescott is a new design on a new process. Look at Hammer on SOI. I kind of expected Intel to do a NorthWood process conversion to 90nm first to get some volume experience but we haven't seen any signs of that happening.
theInquirer reporter used the words new core revision in paraphrasing the Intel exec.
That would be a major stepping and include the base layers. While more involved it's not uncommon.
BTW, while it might be true that Prescott will be as much as 100W at intro, I don't consider TheInquirer article to be an official Intel announcement.
HP releases low-power blade
By Stephen Shankland
CNET News.com
August 6, 2003, 8:10 AM PT
Hewlett-Packard has released a new low-end blade server using Intel's Pentium M processor originally designed for laptop computers, the company said Wednesday, amid an upgrade of its other blade models.
http://zdnet.com.com/2100-1103_2-5060521.html
borusa - My guess is that when Intel processes a wafer defects are not exclusively random. I can further speculate that the ratio of yeild to wafer size is not liniar.
Not exclusively that's for sure but over time and large volumes that's the best model to use. BTW there is reason to think that 300mm defect density will be lower than 200mm. A large number of the particulates come from the equipment, so more or less the same number of equipment related particles will fall on both wafers.
Chipguy - It looks like AMD is not planning to retire the K7 core yet.
I can't see them running 2 processes for long. Has AMD got Athlon running on any foundry's process yet?
YB - So we'll have one more time this year AMD PR singing the "fastest cpu in idustry" song, except that this time, finally, it will be true.
You're doing it again. Comparing AMD's future products with Intel's current one.
RGood - Thanks for saying that.
I was beginning to think that Dan 3 and YBank dont
believe that INTC does indeed have a mask design team.
I think it comes from AMD press releases where they make it sound as if a new stepping is a big deal. I've seen as many as 4-5 steppings in production at the same time and some of those steppings were on slightly different processes or even multiple processes. Intel can do multiple steppings that do not effect logic without the need to notify customers. Speedpath work goes on constantly and customers never need to see the steppings changes. You can bet that AMD is spinning mask sets at a feverish pace trying to enhance binsplits. No need to announce anything if there's no change visible to the customer but you know it's happening as we type.
Cj - Even if that is the case, so what? A 200mm wafer costs what? $50?
OK, now I get it. I was thinking finished wafer cost. You're right. This is inconsequential.
Keith - 300mm wafers cost 10X a 200mm wafer???? I don't believe it.
Sgolds - I'm not an expert in this area either but it seems to me that in the days of the 80486 the buss protocol was entirely different. Today the processor can issue a transaction and there's no need to hold for an acknowledgement plus the address and data lines are not shared. The time needed to notify the other processors that the content of memory location X has changed is the same amount of time it takes to actually go ahead and write the transaction to memory. It's a posted transaction. At least that's the way it looks to me.
Sgolds - Presumably, it is done in a write-back fashion. That means that the processor signals to everyone else that it is about to write a location. Then it is written to local cache. Now this processor is free to use the new value from its own cache while the value is 'written back' to the other processors and main memory. Everyone else has to wait until they get valid values before reading.
Isn't this actually write-through? If you have to waste a buss transaction to make the other processors snoop you may as well write it to memory.
wbmw - Given Intel's gains, Wu said he believes Nvidia is likely to enter a license agreement with Intel to sell integrated chipsets that run on Intel microprocessors.
Yes, I should have noted that too.
YB - After all, current will go down next year, what's the rush?
I can't speak to the MB issues but Intel has a next generation processor that's probably already in production in a fab dedicated to a 90nm process on 300mm wafers. Why wait?
If Prescott will be 100W on 1.1V (say), it will soak 90 A of current, which is enough to kill elephant in 1 sec.
You would have a hard time ramming 90A through an elephant with only 1.1V of potential.
= UPDATE: ATI Tech Falls On Downgrade, Weak GameCube Sales
By Stuart Weinberg Of DOW JONES NEWSWIRES TORONTO (DOW JONES)--Shares of ATI Technologies Inc. (ATYT) are down 7.5% after Wedbush Morgan cut its rating on the stock to hold from buy, citing ATI's rich valuation and the threat of increased competition from Intel Corp. and Nvidia Corp. (NVDA).
Weak GameCube sales by Nintendo Ltd. (J.NTD) for the three-month period ended June may also be weighing on the stock, as may news of Nvidia's $70 million acquisition of MediaQ Inc., a closely held maker of mobile device displays.
On Nasdaq Tuesday, ATI is down 97 cents to $11.91 on about 4.95 million shares. Nvidia is up 3% to $21.06.
"In our opinion, (ATI) is facing increasing threats from Intel in notebook integrated chipsets and Nvidia in integrated chipsets for both desktops and notebook," Wedbush Morgan analyst David Wu said in a research note.
According to Mercury Research, Intel's share of the desktop integrated market climbed to 64% from 57% in the second quarter, Wu said. In the notebook market, Intel's market share jumped to 39% from 25% during the same period, he said, adding that he expects Intel's market share in this segment to increase.
Given Intel's gains, Wu said he believes Nvidia is likely to enter a license agreement with Intel to sell integrated chipsets that run on Intel microprocessors. Currently, Nvidia's integrated chipsets run on Advanced Micro Devices Inc. (AMD) microprocessors, which have a 20% market share, a distant second to Intel. ATI's integrated chipsets are licensed to work with Intel and Advanced Micro.
Wu doesn't own ATI or Nvidia shares and Wedbush Morgan doesn't have an investment-banking relationship with either company.
YB - If AMD go bust, Intel would postpone Prescott until Q2 '04 and do it right. This is very significant change, it must have consequences, as well as reasons.
I think you guys are really over reacting here. So early Prescott gets a 100 watt rating. That's only the top end speedgrade, only a very small % of those will reach that and only at highest Vcc. A stepping is in the works to address this and you'd be surprised how many steppings get done. It happens all the time.
Sorry for the large post but I got it off the news wire and there's no link. Good read.
SGI Leads Effort to Scale Linux to 128 Processors in a Single-System Configuration
LINUX WORLD EXPO, SAN FRANCISCO, Aug 5, 2003 /PRNewswire-FirstCall via COMTEX/ --
SGI (NYSE: SGI) today announced plans to extend the industry-leading scalability of its SGI(R) Altix(TM) 3000 servers to encompass a record 128 processors within a single instance of the Linux(R) operating environment. SGI, which already provides award-winning Linux OS-based Altix 3000 systems that scale to 64 Intel(R) Itanium(R) 2 processors, intends to site-test 128-processor systems with national laboratories and leading universities around the world. Initial results of testing in customer laboratories are expected in early September.
Participants in the global program include in the United States the U.S. Naval Research Laboratory in Washington DC and the Pacific Northwest National Laboratory in Richland, Washington, and abroad, the University of Queensland in Brisbane, Australia, and The Computing Center at Johannes Kepler University in Linz, Austria. The program participants conduct complex research in a range of scientific fields. Their demanding work requires massive scalability at levels that can provide effective and revealing stress loads on the 128-processor system prior to its commercial availability as a standard SGI product.
"In areas of advanced and important Navy research -- such as computational fluid dynamics, climate/weather/oceans modeling and simulation, computational chemistry and materials, and computational electromagnetics and acoustics -- complex problems can literally take months to solve," said Wendell Anderson, Senior Research Mathematician, U.S. Naval Research Laboratory. "With large shared memory systems, such as Altix running 128 processors, we can solve our most complex problems and workloads and save weeks of time because of the scalability and efficiency of the SGI architecture."
"SGI customers are constantly pushing the limits of computing," said Jan Silverman, senior vice president and general manager, Industry Solutions and Services, SGI. "As soon as we launched the Altix 3000 family they asked when we would scale a single system to 128 processors. With their assistance, we are responding to their need for more processing power and all the benefits of NUMA-based computing combined with the benefits of the Linux operating system."
Since its introduction, the Altix supercluster has been recognized as the first Linux cluster to scale to 64 processors within a single node and the first cluster to allow global shared-memory access across nodes. Inspired by the success of the Altix family and the powerful combination of standard Linux on Intel Itanium 2 processors, developers have ported more than 60 commercially available high- performance manufacturing, science, energy and environmental applications to the 64-bit Linux environment. More than two-thirds of those applications have been certified and optimized for the platform.
The 128-processor beta program continues the growing momentum generated by the Altix 3000 family of servers and supercomputers, which earned "Best of Show" honors at its Linux World debut in January and recently was named "Product of the Year" by the editors of Linux Journal. The momentum continued in June, when the Altix family also won "Best Linux Hardware" honors at the LinuxUser & Developer Expo.
Since its introduction, the SGI(R) Altix(TM) 3700 supercluster has been recognized as the first Linux cluster to scale to 64 processors within a single node and the first cluster to allow global shared-memory access across nodes. Inspired by the success of the SGI Altix family and the powerful combination of standard Linux on Intel Itanium 2 processors, developers have ported more than 60 commercially available high-performance manufacturing, science, energy and environmental applications to the 64-bit Linux environment. More than two-thirds of those applications have been certified and optimized for the platform.
Availability
SGI Altix 3000 servers and superclusters supporting the new 128-processor node size are expected to be available as fully supported configurations in spring of 2004, when the beta program concludes. SGI Altix 3000 servers and superclusters supporting 64-processor nodes, in configurations of up to 128 Intel Itanium 2 processors, are available today from SGI. For customers demanding even larger Altix superclusters, SGI expects to support configurations of 256 processors in September and 512 processors in October 2003. Additional Altix system technical and availability information is posted on www.sgi.com/servers/altix.
AMD Delivers Increased Performance to Enterprise Customers with the AMD Opteron Processor Model 246; AMD Opteron Processor-Based Servers Achieve Record-Breaking TPC-H Scores
SUNNYVALE, CALIFORNIA, Aug 5, 2003 (CCNMatthews via COMTEX) --
AMD (NYSE:AMD) today announced immediate availability of the AMD Opteron(TM) processor Model 246, designed to provide outstanding performance for servers and workstations. The AMD Opteron processor Model 246, which will power the IBM eServer 325, provides a unified platform for servers and workstations, enabling simultaneous 32- and 64-bit computing. The IBM eServer 325 is planned to power one of the world's largest Linux supercomputers at Japan's National Institute of Advanced Industrial Science and Technology (AIST).
Recently announced results of the Transaction Processing Performance Council's TPC-H benchmark, which measures business-related database queries, confirm the IBM eServer 325 featuring the AMD Opteron processor Model 246 is currently the highest performing system tested on this benchmark for both 100GB- and 300GB-sized databases.
"The clear increase in productivity offered by the AMD Opteron processor can drive a shift in enterprise and cluster computing," said Marty Seyer, vice president and general manager of AMD's Microprocessor Business Unit. "With AMD64 technology integrated in the AMD Opteron processor, coupled with IBM's eServer 325 product line, IT managers will now have easy access to 64-bit capabilities. The AMD Opteron processor can give businesses and institutions of all sizes a lower total cost of ownership with superior performance."
"Our customers in research-intensive industries, such as oil and gas exploration, pharmacology, finance and higher education, have been eagerly anticipating IBM products based on the AMD Opteron processor," said Dave Turek, vice president of Deep Computing at IBM. "These critical industries often utilize clustering, which demands stability, reliability and ease of management as well as superior computing performance for intense calculations. The AMD Opteron processor is uniquely suited for their needs."
"Tenet HealthSystem is currently running 32-bit performance benchmarks on the AMD Opteron processor and thus far the results have been outstanding," said Rex Conatser, director of IS Operations at Tenet HealthSystem. "The combination of its industry-leading 32-bit performance and 64-bit capabilities offers an exceptional value proposition for any enterprise looking for long-term server investment protection."
AMD Opteron processor Model 246-based servers outperform many competitive offerings by up to 50% on industry standard benchmarks. Complete benchmarking details for the AMD Opteron processor are available at http://www.amd.com/opteronperformance.
Pricing
The AMD Opteron processor Model 246 is priced at $794 in 1,000-unit quantities. For a complete listing of AMD processor pricing, please visit http://www.amd.com/pricing.
About the AMD Opteron Processor
The AMD Opteron(TM) processor is based on AMD's eighth-generation processor core, which marks the introduction of the industry's first 64-bit, x86 technology implementation. This technology preserves companies' investments in 32-bit applications, while allowing a seamless transition to 64-bit computing as those companies require. The AMD Opteron processor is designed to deliver high-performance server and workstation solutions for today's most demanding enterprise applications. The processor is scalable, reliable and compatible, which can result in lower total cost of ownership. Key AMD Opteron processor innovations include an integrated memory controller, which reduces memory bottlenecks, and HyperTransport(TM) technology, which increases overall performance by removing or reducing I/O bottlenecks, increasing bandwidth and reducing latency.
Dell knocks IBM off number three cluster rung
By Tony Smith
Posted: 04/08/2003 at 12:53 GMT
IBM's Opteron-based supercomputing cluster, announced last week, has already been knocked out of third place in the world supercomputer chart, by another cluster that hasn't been installed yet.
Dell today issued a future tense press release detailing its selection as the provider of a 1280-server cluster for the National Center for Supercomputing Applications (NCSA) at the University of Illinois, Urbana-Champaign.
All those Dell PowerEdge 1750 servers, each containing dual 3.06GHz Intel Xeons, will be used to deliver 17.7 trillion floating point operations per second, enough, says Dell, to "rank this cluster as the world's third most powerful system on the Top 500 List of supercomputers".
Last week, Big Blue said the same thing of its 1318-server cluster, which it's going to install for the Japanese National Institute of Advanced Industrial Science and Technology. "It is expected to be more powerful than the Linux cluster currently ranked as the third most powerful supercomputer in the world," said IBM.
IBM's servers are based on dual Opteron processors and Xeons, which together yield 'just' 11.2 teraflops. "The eServer 325 systems with 2116 AMD processors is expected to deliver 8.464 teraflops of processing power," said IBM. "The 520 Intel processors are expected to deliver 2.704 teraflops of processing power for a total of 11.168 teraflops."
So the 36.7 per cent increase in teraflops that the Dell rig offers over its IBM rival, comes on the back of a three per cent decrease in the number of processors: 2560 to 2636.
Of course, such a calculation is very rough and doesn't take into account all the other systems used to complete the cluster, such as I/O service provision machines and what have you. But it's a fun sum.
The NCSA said its cluster will be used to study the evolution, size and structure of the universe; investigate theories on the lifecycle of stars like the Sun; modeling severe storms; studying the human genome and biological processes; advancing the drug design process and more. ®
http://www.theregister.co.uk/content/61/32144.html
Drjohn - Maybe thats why they soundly beat opteron. Also if the total cache is 1meg the die size can't be that big, meaning they are still very profitable for intel.
That other 512K of redundant cache doesn't just go away. This also raises the question of why is half the L3 redundant? I'm not an architect or a design engineer but I might speculate that it is actually the 2Meg L3 design with half the L3 disabled. On the 2Meg version only 25% was lost instead of 50% on the 1Meg version. I wonder how must more performance we'd see if the L3 was fully exclusive? Why wasn't it in the first place? Might Intel be doing a 1Meg version that addresses this issue?
An answer to a lingering question about Intel's 1Meg L3 Xeon DP.
1) The L3 is mostly inclusive of the L2.
2) The Xeon DP 1M L3 and Xeon MP 1Meg L3 are 100% the same in terms of cache behavior.
3) Both run at full speed.
http://intel.forums.liveworld.com/thread.jsp?forum=242&thread=6636
Haddock - I base this on the supposition that Itanium will not be able to beat Opteron's flops/$ figure.
Oh I'm sure they could beat the flops/$ figure but I agree they won't.
Dr J - You are making your posts very difficult to read. You need to change the font between the material you are quoting and your own response. Otherwise we can't tell who said what.
Techman - With Intel already profitable, any increase in volumes would largely go straight to the bottom line. An increase in demand would mean increased profits. For AMD, their ability to produce their products is in serious question so an increase in demand doesn't necessarilly mean anything. In this case Intel should react more favorably to hype however I don't see INTC doubling any time soon:( With AMD essentially priced at book value maybe you're right after all?
Sgolds - I think that things are settling out where Opteron has the leading integer performance for small clusters, and Itanium has the leading floating point performance.
I'd like to know where you are getting this information. In SPECint scores, Opteron loses to Xeon in all benchmarks, single processor and SMP. Xeon beats Opteron on TPC-C scores as well.
Sgolds - I learned to type on a manual typewriter a long time ago. When I first used a word processor, it was very strange to keep typing without hitting the 'return' key at the end of each line. After a couple of years it became more natural to me, it has been a while since I even thought about it.
I think you nailed it. The posts do contain carrige returns and you will see them copied when you do a cut & paste. They need to learn to just keep typing as you did.
Sgolds - That's why Opteron is becoming popular in supercomputer designs - its architecture is optimized to run small clusters faster than anyone else, and at a lower cost. Just what supercomputers need.
I'm sure that was the design goal and it looks like they'll hit it on the cost side but, as yet, they missed their performance target or they misjudged the competition.
drjohn - Austin must be real pleased they are getting a tax consuming Federal jailhouse where they could have had a tax generating High Tech research center.
I'm vacationing in California and every time I go to a supermarket there's someone outside with a petition to raise taxes on corporations. In other news someone is claiming corporations owe millions in unpaid overtime. While so many jobs are disappearing over seas they might as well send business a "get out of California" card. What are these people thinking?