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mmoy,
do you know who makes the panels for the Dell's monitor?
Joe
jj,
Therefore I took a step back and tested it on 3 machines available to me. On a Duron 900 and an Athlon 1700+ the problem is reproduced. However, on an Athlon 2200+ the page loads without any trouble at all...
I guess wbmw's PC is a sub AXP 2200 in performance.
Besides, this could be good for my investment, encouraging web site visitors to upgrade their CPU.
AXP 3200 and A64 3500 work just fine.
Joe
mmoy,
the extended delivery times are for items that are not ready to ship, such as PC that needs to be assempled. For items in stock it is not unusual to have your order shipeed the same day you place the order. So something ordered on Sunday that ships on Wednsday is nothing to write home about.
What you can write about though, is how you like the monitor, when you get it.
joe
Buggi,
Thanks, but I am not ready to buy it yet. I already have an HP 23" at home, I could take it to work and buy the Dell monitor one for home, but I would have to research if Dell is as good as (or better than) HP for things like gaming), and wait until I have someone to unload my existing work monitor to.
Joe
mmoy,
Is that the 2405FPW model? That's a good price. Where did you get the coupon?
Joe
jj,
It loads fine for me using IE.
Joe
chipdesigner,
Newegg has 820 and 840EE in stock:
http://www.newegg.com/Product/ProductList.asp?Submit=Go&DEPA=0&type=&description=smithfi...
joe
fpg,
Thanks for looking it up. It does not mean it is set in stone. AMD can change the implementation in the next socket release and expand the physical addressing capability.
Joe
Mike,
Transition to Rev E core (BP, BN) seems to be progressing well.
Joe
fpg,
No, I don't. It's possible (and maybe even likely) I'm wrong...
Intuitively, I would think you are right. CPU has only 40 address bytes, which can get mapped to any memory location. when it comes to comunication with other CPUs, it is in terms of virtual addresses (I assume). The physical address per CPU should be irrelevant.
But as I said, I have not seen any confirmation about this theory.
Joe
chipguy,
Is it really negligible for AMD given their 32 bit value
chip is a bulk CMOS product? Perhaps the Celeron D
intro is a deliberate tactic by Intel to force AMD to all
SOI production.
I don't think it is entirely accurate. AMD was planning to go entirely 90nm SOI, independent of what Intel does with Celeron.
Joe
rlweitz,
Which show was this?
Joe
fpg,
It is capable of addressing 2^48, and accessing it via HTT.
That's what I was always wondering about, which is whether the limit is per CPU or per system. Somewhere along the way I came across info suggesting it is per 2^40 is per system, not just CPU.
Do you have a link confirming your claim?
Joe
fpg,
If so, the "application accelerator" is a big honkin' FPGA.
Yes, that's what it is. I would hope that AMD would design something that is more manageable and easy to use (program), and still provide a lot of FP performance. Something general purpose could be used as Physics Processing Unit for games, to speed up calculations in HPC market.
Joe
Tenchu,
I missed what will be the fate of Fab 25
Fab 25 is already owned by Spansion, not AMD.
Joe
chipguy,
One of the SGI types who posts at RWT said it was
pretty cool the first time he malloc'd a 2TB chunk of
memory in his test code.
all I can say is: wow! I spend hours and hours working around 64K limit...
Joe
Jules,
AMD uses 2 differend depreciation schedules. One for tax purposes is based on what IRS says, which may or may not correspond to useful life of the equipment.
But for earnings purposes (GAAP), AMD uses schedule that reflects useful life of the equipment.
BTW, the section of tax code is I believe Section 179, but it is all but useless to company like IBM, with 100s of million in capital expenses. It is great for small businesses, as most of the capital expenses can be written off immediately.
Joe
Klaus,
When Fab 30 is due for upgrades, will be when Fab 36 is fully ramped, with capacity of 2.25 of Fab 30 and with Chartered or IBM available to manufacture additional processors for AMD.
If the upgrades causes any problems to AMD in terms of being able to ship enough parts, it will mean that AMD market share is around to 30%. So this will not be a problem, but a cause for celebration.
Joe
Klaus,
I like the "Saxonian Ping-Pong" analogy. It is not feasible though imo. Playing this game would only allow for amortization periods of three years or so.
What makes you say 3 years? Fab 30 is entering 6th year of production, and will be in production at minimum another year and a half before an upgrade can take place (= 6 1/2 years).
Joe
Alan,
Here is twenty of them, all in the same cluster
each group of 512 cpu's has 1TB of memory
I should have asked: "How many sold with > 1 GB of memory?"
Joe
Opteron dominates 4 way SAP scores. Top 3 scores. Also, 7 out of top 9 scores.
ftp://ftp.compaq.com/pub/products/servers/benchmarks/pl-sapsd.pdf
Joe
Smallpops,
IIRC that the average Altix size is around the number that you posted. However Altix(IPF) has another major advantage over current Opterons and thats the address space. Opteron is currently capped at 1 TB and IPF can go to a very much larger number whatever 2^50 is I believe. Also its possible to add memory to Altix without adding procs, this is not possible with current Opteron systems.
How many systems do you think sold with 1 TB of memory? 1? More than 1?
If HP is in fact going after HPC market with Opteron, isn't it enough of a first step if the system you offer is good enough for 90% of the market?
Also, the trend to clustering solutions is continuing from very large systems.
Joe
b2l,
Do you know how much info the foundries give the customers reguarding inline data. I cant imagine having a chip at another fab without being able to react to daily yield surprises and being part of the task force to solve. Quality will suffer.
I am not really even counting Chartered. The demand for Chartered will be for Venice chips that can reach clock speeds of 1.8 GHz to 2.0 GHz. If AMD is about to reach 2.8 GHz for the same parts, is it unrealistic for a foundry to reach speeds I mentioned?
As far as capacity, Fab 30 capacity is probably for 10 to 12M 90nm units of current mix (My guess the sales last Q were 8 to 9M, is that the right ballpark?). If Chartered were to relieve AMD of a chunk of the Sempron sales, and Fab 30 stuff is more dual core based, Fab 30 can still produce some 7M parts that are 50% or more dual core, the rest high end of the clock speed spectrum, single core (2.2 to 2.8 GHz).
And that still leaves Fab 36 out of the picture, which may by the end of the year be capable of out-shipping Fab 30.
So AMD needs design wins between now and the end of the year. Since the wafer starts are near 100% 90nm, and shortly, they will be nearly 100% Rev E, inventory control should not be an issue (since the chips will be saleable for a long time), and AMD should now be building up some inventory for the design win push for H2.
Joe
Buggi,
It looks like AMD is pricing the Socket 754 Athlon 64s to sell. I guess Socket 754 is going to be discontinued for Athlon 64 line.
Joe
UND,
You've got this all backwards. AMD is going to play ping-pong with their Dresden fabs. All low-cost, volume production will be from Chartered. Once Fab 36 is up and running, Fab 30 becomes the site for new development.
That is my take as well.
All I am wondering about is how (or if) AMD can sell all of this huge capacity that is coming online in 2006.
Joe
UpNDown,
Verrrry interesting. First analyst day they've ever held before market open, as far as I can remember. Must be to make an announcement without halting trading. Could this be? No, I can't say it. ***l?
No, this thing was scheduled for a while. IIRC, it was announced during the quarterly CC.
BTW, I was wrong It is not going to be technical, it will be financial:
-------------------------------------------------------------------------------------
SUNNYVALE, CA -- June 8, 2005 --AMD (NYSE:AMD) today announced that it will hold a financial analyst meeting at approximately 9:00 a.m. ET (6:00 a.m. PT) on Friday, June 10, 2005 in New York. AMD President and Chief Executive Officer Hector Ruiz and members of AMD’s management team will deliver key presentations regarding AMD’s microprocessor business. Forward-looking and other material information may be discussed during the presentations.
-------------------------------------------------------------------------------------
As far as being before market opening, this thing may last for a couple of hours.
Joe
T64,
HP should just buy Cray and use their tech...
I am not sure there is anything Cray does that HP can't do independently, with lower expenditure than taking on Cray.
My guess is that future Opterons will be more HPC friendly out of the box, possibly eliminating the need for various custom ASICs that Cray is using.
Joe
chipguy,
If that story is true it tells me HP doesn't want to lower
Integrity server ASP by taking on Altix, Power5, and x86
directly in HPC with its flagship commercial server line.
It may also be the case that economics of the Integrity line does not allow HP to be very aggressive in their bids, and Opteron offers a much cheaper, more price competitive option.
HP system does not need to compete across the spectrum. If they can come out with very cost effective 4 to 16 socket (possible 32 socket) system, it would cover a good chunk of HPC market.
If the side effect is that it contributes to SGI going under, it will only help HP, so that they are trully the only viable choice for Itanium based systems.
Joe
SmallPops,
a 32 socket system doesn't even begin to enter on SGI turf.
Not the Altix 3000 line at least. Maybe the smaller 350 line.
The Altix 3000 line can scale to 10,000s of cpus and IIRC they are already at 2048 procs in a SSI and going higher!!
If you look at their wins:
http://www.sgi.com/company_info/newsroom/press_releases/2005/april/fy05_q3wins.html
http://www.sgi.com/company_info/newsroom/archive/2005.html
you will find a large number of sales to be 32 processor and under. Now, Opteron is now dual core, going to quad core, Itanium is going to dual core + CMP, so you can get 2 to 4x of bang out of each socket, reducing the need for sockets to get comparable performance (therefore expanding the horizons of potential HP entry to the market).
Then, who says that the scheme HP goes with, if it can go to 16 or 32 sockets, who knows if it cannot be expanded to more sockets? What's the limit of Horus, BTW?
Joe
chipguy,
What's your take on HP possibly entering SGI turf?
http://www.theinquirer.net/?article=23745
SGI seems to be barely keeping afload as is.
Joe
chipdesigner,
thanks for running the numbers.
If they can pull off a shared cache, that would be nice, though.
I think that would have to bart of the revamped CPU (which is due anyway.
A few things going on, IMO is going to be a trend to reduction of CPU sockets. For that, something like FBDIMM use will be a necessary thing, since currently, 2 channels of DDR(1 or 2) produces some limitations, when you want to have a number of DIMMs pe channel.
For example, 4 socket single core system, like HP DL585 gives you all the headroom you need, either with 2 DIMMs per channel or even with 4 per channel (with reduced bandwidth), since you have 8 channels.
Now, when you go to dual core, all you need is 2 socket system to get equivalent performance, but this will result in a loss of 1/2 of the memory channels (loss of total memory capacity).
With these > dual core processors, even a single socket system will give you a tremendous bang, but you need memory to go with that, and FBDIMM may come in handy. 4 channels of FBDIMM per CPU socket may be feasible, 4 memory channels of DDR (1 or 2) is proabably not feasible.
Then, next thing that will need to be re-vamped is HT. HT 2.0 at 1.4 GHz with 32 bit per direction may be necessary (2.8x increase from current 1 GHz, 16 bit per direction).
And, as I said, shared cache may be necessary to go in direction of an array of (variable number of) small cores. The cores need to be small. Taking out L2 would seem to be the way to go.
One (side) benefit of say 1 x 4 MB L3 vs. 4 x 1 MB of L2 is that when running a single thread, one core has 4 MB of cache available.
Joe
Rink,
How about making something like this part of the processor:
(the application acceleration part).
It would be nice if it was possible to have some kind of simd core shared by all cores, which would not need changes to ISA though. What Cray has is of limited use (I think it is an array of 18 bit multipliers and it needs special programming).
Joe
chipdesigner,
My guess is that AMD will be moving to shared L3 (L2), probably getting rid of L2. The core, even under 90nm is probably in 40mm^2 ballpark (without L2, memory controller, HT and DRAM interfaces, so it may be possible to do 4-way under 90nm, with modest shared cashe of 1 to 2 MB, and end up in 300mm^2 ballpark.
Maybe AMD should put 5 cores on the chip and disable 1. Those IT folks' brains may enter an endless loop if AMD tries to sell them 3-core CPUs.
Joe
Keith,
This is "technology" analyst meeting, rather than "financial" analyst meeting. This is the first one for AMD as far as I know, and I believe.
When someone asked AMD some time ago if AMD is going to have someting like IDF, AMD answered that they are planning something. This seems to be it. It will be on much smaller scale, but I really appreciate AMD holding it.
I don't know about you, but it seems to me that right now, we are at the point when I know the least about AMD plans, near or longer term plans. So this meeting is really needed, since the flow of info about future plans all but stopped.
So, it may be a very exciting day on friday. Maybe we will find out about K10 plans, ORNAND status, Fab36 update, and about the rumored 3 way processors...
Joe
Lol. Maybe Tom will start late night infomercials: Gain financial independence through benchmarking...
Joe
I think it's a spoof, but it might have looked that way when one of the motherboards wend up in smoke.
Keith
Hopefully, we will get an updated roadmap that goes further than the current one, which goes only 6 months out.
Joe
It has been on Microsoft site for long time. I posted some links on SI a few weeks ago.
The only one people seems to have noticed is the one which implies that microsoft.com is now running on Opteron servers.
Joe
mmoy,
8 registers is claustrophibic. I'm itching to try playing with 16 registers though.
Do you mean that you want 16 registers in 32 bit mode? I am not there is any point in changing something like this at the time when 32 bit mode is about to start its decline, and software development starts to move to 64 bit mode.
Joe
I_banker,
I think there is a lot of room to improve performance of SSE-X which would not require changes of the instruction sets, and there may be room to extend it with more instructions or wider registers. x86 world is very evolutionary, not revolutionary.
Joe