Advanced Micro Devices Inc (AMD)

[jhalada]

chipdesigner,

thanks for running the numbers.

If they can pull off a shared cache, that would be nice, though.

I think that would have to bart of the revamped CPU (which is due anyway.

A few things going on, IMO is going to be a trend to reduction of CPU sockets. For that, something like FBDIMM use will be a necessary thing, since currently, 2 channels of DDR(1 or 2) produces some limitations, when you want to have a number of DIMMs pe channel.

For example, 4 socket single core system, like HP DL585 gives you all the headroom you need, either with 2 DIMMs per channel or even with 4 per channel (with reduced bandwidth), since you have 8 channels.

Now, when you go to dual core, all you need is 2 socket system to get equivalent performance, but this will result in a loss of 1/2 of the memory channels (loss of total memory capacity).

With these > dual core processors, even a single socket system will give you a tremendous bang, but you need memory to go with that, and FBDIMM may come in handy. 4 channels of FBDIMM per CPU socket may be feasible, 4 memory channels of DDR (1 or 2) is proabably not feasible.

Then, next thing that will need to be re-vamped is HT. HT 2.0 at 1.4 GHz with 32 bit per direction may be necessary (2.8x increase from current 1 GHz, 16 bit per direction).

And, as I said, shared cache may be necessary to go in direction of an array of (variable number of) small cores. The cores need to be small. Taking out L2 would seem to be the way to go.

One (side) benefit of say 1 x 4 MB L3 vs. 4 x 1 MB of L2 is that when running a single thread, one core has 4 MB of cache available.

Joe