Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
looks like Montecito cache hierarchy to me (without L4)
*ducks*
Aha ... Intel said that only Nehalem "fully unlocks Intel 45nm Hi-K silicon process benefits"
btw, that was a quote, not from me :)
The stronger pFET is causing Intel’s design teams to consider the mix of NOR gates, which rely on the nFETs, and NAND gates, which are more pFET-dependent. "With a higher beta ratio [between n- and pFET performance] of 1.3, we can tell our designers up front so they can take advantage,” he said.
Intel Takes 45 nm HKMG Process to IEDM
http://www.semiconductor.net/article/CA6512230.html?industryid=47298
mas,
could you post some link .
searching for "Conroe TLB Dell" turns up nothing ..
AFAIK, it was just that intel "clarified" their TLB behaviour for core 2 , and never plans to fix it in any stepping ...
the patch is just for windows that is expecting the old behaviour ..
wow i'm speechless
pgerassi and kpf .. twins separated at birth ?
btw .. Stephen Fisher (lead archtiect of penryn) said , when asked, that there are currently no plans for a single core penryn ..
i wonder why he did not say "it's called silverthorne!"
Silverthorne is based on the 'Bonnell' core.
-Justin Rattner
http://www.careers.eweek.com/article/Intel+CTO+Rattner+Talks+Nehalem+Virtualization/215587_2.aspx
UPDATE :
Intel perfomance primitives support "Bonnell family" of processors
http://softwarecommunity.intel.com/isn/downloads/softwareproducts/pdfs/272671.pdf
6-Core Dunnington with 16 MB L3.
spotted on RWT board.
Also has the codename "Mill Brook" for the FBDIMM->DDR3 microbuffer. So I guess Goto has some inside information.
http://pc.watch.impress.co.jp/docs/2007/1018/kaigai394.htm
directory cache ?
i guess the huge middle part of the die is the router + directory cache..
(http://www.realworldtech.com/page.cfm?NewsID=361&date=05-05-2006#361)
-----------
btw
slide 10 here had Tukwila die schematic for a few months ..doh
http://download.intel.com/pressroom/kits/itanium2/Itanium_pressdeck_061407.pps
Not much better than the photo, tough
leakier Harpertown SKUs are also coming.
http://www.vr-zone.com/articles/New_Harpertown_Model_&_Pricing_Updated/5300.html
either Penryn is not as good as expected or they simply want to ramp 45 nm quite hard.
it still might beat a 2.1 ghz* barcelona in specfp ;)
*)5 and 10 % lower mem performance than 1.9 ghz and 2 ghz
With Nehalem, we will then have 8, 7 , 6 , 5 , 4 , 3 , 2 , 1 core products, each with HT enabled/disabled .. enjoy !
quick mas,
you could apply for the job !
the split happened so "amicable" that they don't have a replacement in place.
Wolfdale 10 % slower in one subtest
(Sysmark Video Creation)
Conroe : 109
Wolfdale : 101
so either some optimization backfired on this particular benchmark or "A0" really has some small performance bugs ..
put's a question mark on the other results as well..
Tigerton shipping since June
"best execution we've ever had from design to production of a multiprocessor architecture"
http://blogs.intel.com/views/2007/07/caneland_caneland_everywhere.html
so it's beating Barcelona by at least two months...
At the least it seems to steal some blade design wins away from AMD.
those leaky barcelonas :
they could disable 3 cores, clock them to 2.3 ghz and sell them as semprons ...
Intel is brutal..
half-step multipliers and no cache reduction for the low end models..
E5410 will have Barcelona in check ..
maybe even the E5405 ($209)
it's the worst TPC-E score ever submitted.
Intel is doomed !
no impact from Barcelone in 2007 ?
didn't Hector Ruiz say that Barcelona would have no material impact in 2007, only "design wins"..
how can one reconcile this with "revenue shipments" in August ?
When is Beckton due? Is it 65 or 45 nm?
---
No idea .. If Beckton is here soon,
a rebadged Harpertown (Dunnigton ?) might be the last Xeon MP on FSB..
pretty boring but probably good enough..
8 MB dual core tigerton
the dual core tigerton has 8 MB cache .. so it's actually two Woodcrests with one core disabled each !
With Penryn, Intel might go further.
Release quad-chip-module Xeon MPs
- as oct-core with 16 MB cache
- as quad-core with 16 MB cache.
the 6 MB cache of penryn would need to be cut to 4 MB to fit into the 64 mb snoop filter of the Caneland platform.
But maybe they've got something "Tulsa" like coming for Xeon MP.. a monolithic dual core die with separate 2 MB L2 cache and unified 8 MB L3 cache.
These are strange beasts, but Intel has to offer some long-term pespective for the Caneland platform even with CSI around the corner.
"Tell your contacts to think again until they come up with a safer saner solution."
Maybe a 5-core tukwila ;)
oh my god, mas, seek help.
it's hard to tell in this virtual world, but I think your mental health is really deterioating in recent times.
where's Hector ?
"if you cannot bring good news, then don't bring any"
"Sandy Bridge" vs. "Gesher"
In Intel's latest tick tock roadmap, Gesher was replaced by the Sandy Bridge codename.. so maybe gesher is now mobile only and the Intel U.S team is responsible for Sandy Bridge.
Edit: just read that it was a name change only, for political reasons.. http://www.reghardware.co.uk/2007/04/17/intel_gesher_sandybridge/
the P1265 process, I forgot about that.
I'm not totally sure that Intel will use it for high performance chipsets ... I think it was ment for XScale.
Anyway, if Bearlake and Montevina(Santa Rosa follow up) are on P1265, that's good. every watt helps for power consumption comparisons.
Bearlake chipset preview
on page 2 it says that Bearlake MCH is on 65 nm process ... i was expecting this to be still on 90 nm . We'll know more once Cebit starts.
http://www.tweaktown.com/articles/1062/2/page_2_bearlake_chipset_details/index.html
"You don't see the obvious contradiction?"
They have to relabel a lot of FedEx packages from "Michael Dell" to "Reseller Mike" .. that takes a few months.
some random AMD link so i don't get banned:
http://money.cnn.com/2007/03/06/magazines/fortune/fastforward_amd_intel.fortune/
Do unto others ...
Otellini talk: http://phx.corporate-ir.net/phoenix.zhtml?p=irol-eventDetails&c=101302&eventID=1473681
hightlights so far:
- Santa Rosa in April ? ("in a month")
- in the future, much more silicon on generation n ( 45 nm ? ) than n+1 (65 nm ?) .. may use n+1 generation as foundry
- 1000 engineers working on ultra low power Intel architecture.
- Linux/Firefox for ultra mobile internet
- Pentium 4 was only depature from tick tock model ("shame on us","mea culpa")
- 5 SoC projects going on
So maybe Tukwila was restarted at 45 nm ? :)
Oh, sure, we are supposed to listen to the half hour thing so you can get the three second update
Actually, I was too afraid to register because I'm not yet an Intel investor (soon ..)
Yes I'm that pedantic :)
Any news from the Mobility Group presentation ?
http://phx.corporate-ir.net/phoenix.zhtml?c=101302&p=irol-presentations
nome de guerre might be more fitting :)
I was refering to Mark Bohr in the "tour of D1D" video.
"We were running 65 nm production up until about a month or so,
and are now winding down 65 to make room for 45".
So it's not totally clear, but sounds like "convert at once"
D1D was producing 65 nm until December 2006
and is now being converted to 45 nm.
"is a development facility"
it's not like D1D is a little shack..
it is producing commercial wafers, too.
on intel's feedrom you can find a video tour of D1D with Mark Bohr.
Re: Sweet
Yes, and the Deutsche Bank analysist asked the most important question: "Is 1600 MHz FSB also for quad-core ?"
Answer: Yes
3 GHz Clovertown
1600 MHZ FSB, HPC optimized chipset
pdf slide 13
http://phx.corporate-ir.net/phoenix.zhtml?c=101302&p=irol-presentations
thanks to Golfbum for making me look at intel's inverstors page
45nm pull in
http://uk.theinquirer.net/?article=37775
45 nm Xeon H207 (so maybe even late Q3)
tick tock...