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bobs
Looks like political pork to me.
Well, I agree a mention of the compute-CPUs would have been more adequate than a quote of Intels German head to make a balanced portrayal.
K.
Rink
In a HPC architecture the restrictions of HTT-channels do not apply.
These 750 Itanium2 (1500 cores) are exclusively utilized for memory management. The compute nodes of the system are Opterons in a cluster, but for HPC architects this of minor interest and does not even need a mentioning describing the system.
Here is a description of the system targeting the public: http://www.linuxpr.com/releases/8076.html
K.
Pricelist changes (stealth)
http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_609,00.html
K.
Rink
Yes.
http://www.investorshub.com/boards/read_msg.asp?message_id=7542501
Halfway related to memory management, I recently had a chatter to a development guy from EMC in Ireland. He told me EMC has bout 40M CPU utilized in its storage systems out there. On the question about AMD as a supplier he claimed a lack of support from AMD side versus Intel prevents them from doing more with it. I asked if he was referring to "support" in form of workshops in Switzerland and Tahiti, which he denied. More like Intel is collaborating better in designwork, in personal contact.
K.
Here's some background about the project at TU Dresden
http://www.supercomputingonline.com/nl.php?sid=9202
K.
doug
Thanks. Additionally, XBOX looks like a designwin of the Pyrrhus kind, assuming running 90nm production wafers in an neonatal process stage is what ATI needs eight-digit writeoffs for.
K.
Keith
Ati says it will fall short close to 20% of already reduced revenue expectations. Soft back to school does not explain such a landslide.
Maybe sb listened to the CC and can comment.
K.
Keith
Probably not a general demand weakness. I did not listen to the CC today, but to their last quarterly report. Manufacturing woes, I would guess.
K.
bobs
I would consider Dresden as undisputed AMD territory.
Actually, I believe memory management is an application where Itanium could very well be the cpu of choice from a pure technical viewpoint - as every performance demanding application without codebase considerations.
In essence, any eventual political consideration for the processor choice made for the Cluster around Altix shared memory architecture would be almost certainly in favour of AMD imo.
Nevertheless, the public perception will likely be as I pointed out in the former post. For good.
K.
bobs
Here we are: AMDs cores provide a niche for Itanium2 to keep the memory up to its computing pace....
K.
Keith
I believe SUN needs an architecture capable of scaling up AMD64 to offer a reasonable migration path to its customers from bottom to top from Sparc to AMD64, which is what I believe Andi is currently working on by means of Galaxy.
Wrt 1-way rack servers I strongly doubt it would make much sense for SUN to put effort in challenging low-margin bottom-feed segments where CPU performance is not an issue anyway - a Celeron-box is good enough in many cases. I neither see a position for Opterons nor for SUN there.
K.
chipguy
But at some point Sun is going to have to ditch its MPU
design team.
Well SUN already moved several dozen of design engineers to AMD last year. And SUN was vocal to play a more active role in AMDs MPU designs going forward as well. Sparc Codebase out there allows for a transition from Sparc to Opteron over five to ten years (actually it more demands thinking in this timeframe). I see more a continuous shift of [human] design ressources than really ditching folks at some point.
K.
Keith
What are they thinking???
Along the line of "You can have it fast - or excellent?"
Hurricane took three years to develop...
K.
I_banker
I was implying an IPO before year end, consequently prospectus on the table by Q3 reporting date in two months time.
K.
Chipguy
Interesting. Many thanks.
K.
Keith
Hmm. "Turnaround" sounds too strong for my ears for the recent (admittedly encouraging) NOR tidbits. Actually, the best I expect from it is a Hector-statement along the line "the worst ist over" in two months time.
K.
Chipguy
Thanks very much for the primer on issue width. However, I did not run into any "good evidence" of Merom/Conroe being an architecture basically different from Yonah - which, if I understand it right, would be necessary for different issue width, right? Can you specify which "good evidence" you see pls?
K.
Keith
Spansion does not fab 8Mb Mirrorbit products afaik.
K.
mas
Conroe is supposed to be a quad-issue processor unlike the tri-issue Pentium-M/K8.
Could you pls elaborate on tri-issue/quad-issue architecture?
Tia
K.
I didn't know that.
Are 1xx Socket 939 1xx Opterons differentiated technically from Athlon64, or only by label?
K.
Rink
Maybe, at some point down the road. Knock on wood .
K.
Keith
Enthusiasts should love this, but it doesn´t make sense. Opteron as the cheaper A64 alternative?
While pricelist prices differ a tad, street prices are different, and this is what enthusiasts are looking at. Beyond, system prices will still be higher for Opteron Systems, as ecc memory is more expensive. And you have a performance penalty for using ecc DRAM as well.
K.
bobs
With support from MSFT coming in Longhorn this seems like a natural for Spansion?
Hardly. NOR silicon is about three times more expensive to make than NAND per bit, and will be so for at least the next two years. I can well image usage of flash where erase cycles and error correction considerations make NOR advisable, but only in niches.
K.
b2l
...but who owns the IP and thus in some extent controls the market.
Any change of ownership at Saifun (btw AMD has shares in there) would not affect the licences of its IP.
Apart from that, I am very confident AMD is long enough in the business to make no silly mistakes in essential licence agreements, as well.
K.
b2l
AMD's flash portfolio is mainly based on NROM
Not really. AMD is working on NROM for half a decade already and only last quarter had a fifth of its output NROM based. (actually I believe this is bitshipments). Going forward, floating gate migrates to 90nm as we post, MB a node behind to 110nm, so for the next couple quarters there is always a fallback if NROM continues to be the tough challenge in terms of manufacturability it always was and still is.
I would not put the risk of NROM significantly higher than of Intels Multi-level technology (where basically the same applies as for NROM vs. FG). NAND cost path looks scary - for both of them.
K.
Done. K. eom
Keith
While 8,9M is arithmetically correct for Mercury end markets, this figure must not be confused with CPU shipments of AMD in the quarter, to be determined plus(??) or minus(imo) channel inventories from there. (OEM and retail below distributor level).
Looking at Mercury data in general versus IDC and Gartner, their numbers are doubledigits higher. Can sb confirm Mercury includes Console-Chips while IDC/Gartner don't? (Would be the easiest explanation for the delta in dimension, and comments in the Osha commentary point to it).
K.
burn2learn
Great. Thanks very much in advance. The information you kindly will provide should allow to understand Gartner and IDC numbers better.
K.
Tenchu
I do second this assessment.
K.
Given that after H105 we're at about 17-18M (8.5-9M/Q), shipping 12M in Q3 and Q4 would only put the 2005 total at 41-42M.
I believe this is arithmetically right.
K.
Chipquy
Yup. Actually research data are only meaningful if supplied together with the methodology. As long as it does not change, periodical comparisons of data are meaningful as well. Thing is, methodology does change quite frequently, e.g. which boxes are counted into the serversegment. The ASP and unit relations somewhat point to the difference between Gartner and IDC figures is more there as in their panels.
K.
chipguy
There must have been a significant shift towards the fourway segment at SUN to explain the sharegrowth of Opteron-based systems last quarter (which it claims on slide 27): SUN had some 50% growth on the unit side while AMD had some 90% growth on the CPU revenue side, qoq respectively.
AMDs claim of 27% fourway share in U.S.A. at some point fits in there.
K.
pfosse
I share your outline of AMDs strategy in terms of development and production wafer capacity.
With regard to the Inq piece, Merom is 64bit and dualcore, so these 20-30% performance over Banias are nothing to be really surprised about imo. AMD is not exactly a standing target these days, insofar I don't think folks in Sunnyvale are overly scared of Merom in terms of performance.
Catching up in manufacturing nodes for AMD anytime soon seems optimistic for me - avoiding to fall back further might be more appropriate. Consequently, Intel will probably use its lead there to force AMD into quadcores already in 65nm node by fabbing such a design in 45nm to maintain cost advantage.
K.
pfosse
While I think you described pretty accurately why wafer capacity limited the steepness of AMDs learning curve into 90nm volume, your conclusion seems to lack considering the very same fact: Every development/pilot wafer you run in Fab 30 to accelerate migration AMD means one production wafer less.
Takeaway: Capacity translates to technological pace.
K.
Keith
I assume you refer to Bob's statement in the Q&A of CSFB presentation end of 04. I believe he just tried to save Michael Masdea's face with it, basically saying the 50M number MM postulated is not impossible, however the real number depending on the actual mix. Insofar, I put it into the drawer for meaningless speech-balloons.
K.
Sure. I did not suggest anything contradicting these assumptions.
K.
Keith
I trust AMD´s estimates there.
Me too. Guess we differ in interpreting Daryls Die Output Chart.
K.
Keith
K7 die inventories drying out over the next couple quarters, K8 output from fab30 good enough for uptrading, but not enough to serve low-end value segments as AMD traditionally did. In essence, dollar share gains, unit share losses in H2 05.
In essence: AMD is about to break free from the "value cage" by means of manufacturing strategy, supported by means of the "suit" campaign.
Good to see. However, the sacrifice of unitshares is not deliberate but inevitable imo.
K.
Keith
I agree in everything after the last comma.
K.
Chipguy
Thanks. Suggest we leave it there.
K.