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Possibly, but that would come with strings attached. Hence my earlier comment about customer NRE, which could be put towards not only product but also process development (but without strings attached on the process side).
When that happens we're all monumentally fucked
Silicon photonics will not be a concern (there's good capacity in the US, EU and other parts of Asia), but for CMOS that's a huge exposure, which is why TSMC is busy building fabs outside Taiwan (incl. a $40B investment in Arizona if I'm not mistaken).
The main point I was trying to make is that because - other than Intel - none of the major chip/module/equipment vendors in comms have their own fab, acquiring a company such as LWLG is not a natural fit, but they could work with their respective foundry partners instead to ensure access to the tech.
In the indium phosphide space the situation is a bit different though, think Infinera, Lumentum, Coherent...
Alright 1 final thought for the day - I think the choice to partner with a smaller specialised foundry is the right one. Yes they are small but they're a credible player. With such a partner at least you get the time of day. Show that your stuff works in one foundry, port it to another one as a second source and then for these communications markets you're set volume-wise.
Please put to bed this notion of 5/6/7 foundries - it would be completely unnecessary and an utter waste of resources. All this process development is on LWLG's dime at the moment and does not come cheap.
Technically speaking it's the patent office's job to verify that any new patent application is not already covered by an already granted patent and reject or require amendments to applications that do not pass muster. Clearly this process is not perfect and in fact patents can be challenged even after having been issued. The more nefarious case is when somebody is simply infringing without given any indication of doing so - it's then entirely up to the infringed patent's owner to demonstrate that. This is often not practicable.
Genuinely have no idea but "deal" is a pretty broad term - one thing that's puzzling is why so far there never seems to have been any NRE-based revenue. Does anyone have any insight into that? Was that a strategic choice to not pursue? An agreement to (co-) develop a chip counts as a deal, even if there's no upfront commitment to take it into production.
Takeover - the big chipmaking companies are all fabless, with the notable exception of Intel, who is now clearly separating out their foundry business as well. The big transceiver assembly houses are also fabless and generally just buy the components or develop based on foundry offerings. An acquiring party would probably be either a SiPho foundry, one of the more vertically integrated players in communications who would know what to do what a new material, or indeed an actual materials company.
No, that's not at all what that means, how do you get to that conclusion?
First, O-band is used predominantly for the shorter reaches uo to 10km (mainly 500m / 2km PSM and CWDM). For longer distances C band is more suitable because of the lower attenuation.
Second, all competing technologies also work in the O band (with the possible exception of VCSELs although there are R&D results in that area).
No worries! Should be no problem to port to O-band, some components need to be adapted, but from the underlying physics the key Vpi*L metric should inherently be somewhat better (lower) at the shorter wavelength.
can't quite find the post but I recall someone asked about having a "moat" based on poling-related patents. Tricky one - patent enforcement requires detectability of infringement. While it may be possible to detect that a wafer or PIC has a polymer on it and that the polymer has been poled, it'll be hard to detect unequivocally how the poling was done. It's a balancing act between protecting IP through patents versus keeping it completely hidden as trade secrets.
If you can hit the required average optical transmit power, modulation amplitude, and eye quality as per 802.3dj with sub 1V peak-to-peak drive amplitude, then that is in the cards, yes.
The test setup diagrams from recent talks showed a C-band laser and indeed an EDFA (erbium-doped fiber amplifier). That's pretty typical and not a reason for concern as these bench top setups generally have excess loss that in the final system you would not have (e.g. because light is coupled in and out through grating couplers instead of edge couplers, and there are several optical power splitters). The amplifier boosts the power level but does actually add some noise as well.
They'll need to confirm these results in the O-band. Also the current modulators appear to be single-ended (GSG electrode configuration). A differential version (GSSG or GSGSG) would be a big step forward because that's what most implementations use as of now. Plus of course the inclusion of a low-loss fiber coupling interface. Wirebond should still be OK but some customers may ask for a flip-chip solution.
Assuming said PIC meets the specs (optical, electrical, mechanical), the customer could integrate it in a prototype 800Gbps transceiver module, along with all the other componentry (DSP, laser, driver, TIA, PDs, microcontroller) and run test patterns or even live traffic over it. That's what you really want to get to.
What KCC is referring to is single dies with multiple modulators on them, i.e. a 4-channel modulator implemented on a single PIC. That's what the product should look like and what the customers need to build transceiver prototypes.
As the stated objective is a 4x200G PIC for 800G/1600G IMDD pluggable transceivers, it has to be O-band. This is not the same market as AOCs by the way, which are usually based on VCSELs (850nm).
C-band is for longer distances, usually coherent + WDM. No inherent reason this market could not be serviced, but it's a quite different PIC architecture implementing dual polarisation IQ modulation. There has been some talk about coherent O-band communications for shorter reaches, but nothing too concrete so far.
This is one gap that requires clarification, as it appears from the recent presentations that the device experiments they showed were conducted in the C-band.
Right now, LWLG is a customer of AMF, not the other way around. Presumably LWLG owns IP to certain process steps specific to addition of the polymer, poling, and modulator design. It doesn't seem to make sense to sell the polymer to AMF only to buy it back at a markup as long as all those wafers go back to LWLG.
This changes of course when this LWLG-enabled process becomes available to third parties through AMF, in which case LWLG can start collecting royalties.
Through packaged modulator sales by Polariton, that is likely the case.
OpenLight is based on the Juniper / Aurrion heritage of integrating 3-5 on Si, so this all makes sense. The fab is Tower, but the process is reportedly different from Tower's open foundry offering. Best to partner directly with Tower as an add-on to the standard foundry offering, IMO.
Of all the silicon photonics platforms, this is among the hardest to integrate with because it comes with a CMOS stack on top.
No, this is a silicon-only solution. I'm sure Marvell (like many others) is evaluating alternative modulator technologies though but for the next speed (400Gbps per channel).
I'm reading that as the list of parties that visited the OFC demo.
No, I don't think so. There are plenty of other companies to carry this torch - If SEV fails, their IP and/or engineering team will likely get picked up by a current competitor or someone looking to expand vertically. ACC remains a bit of a niche though.
Great article providing insight on how Nvidia builds their GPU clusters: A closer look at Nvidia's DGX GB200 NVL72.
Not sure if this has been posted here: OFC take-aways / GazettaByte.
Interesting perspective from Chris Doerr, unsurprisingly slanted towards sipho as he was formerly with Acacia - this view does not align with what many others were saying for 400Gbps per channel: "For 200 gigabit per lane, there were many demonstrations using EMLs and quite a few using silicon photonics. Most of the silicon photonics demonstrations seemed to require driver ICs to overcome the reduced modulation efficiency, sacrificed to achieve the higher bandwidth. Consequently, most companies appear to be throwing in the towel on silicon photonics for 200 gigabaud (GBd) applications, instead moving toward indium phosphide and thin-film LiNbO3 (TFLN). This is surprising.
This author strongly believes in the trend usually followed by silicon electronics in that innovation will allow silicon photonics to achieve 200GBd. It is unreasonable to expect indium phosphide or TFLN to meet the volumes, density, and pricepoints required for 3.2-terabit modules and beyond."
Keep in mind that -3dB modulator bandwidth is never the full picture - judicious driver and DSP design can compensate modulator shortfall to an extent esp. if you're Intel, Marvell, Broadcom, etc. If the transmitter meets OMA, ER, TDECQ specs you're good to go. Standard (direct-detect) optical interfaces at this channel rate are still PAM4 (see IEEE P802.3dj); the SNR penalty associated with higher-order modulation is too high in practice. Academics like to play with this, but so far PAM6 and PAM8 have not made it into high-volume products.
They sold the module business, not the sipho part. Intel is still in the business of making PICs for transceivers.
Excellent question, I would need to double check, but I believe this demo was "standard" MZM for pluggables, whereas the ring-assisted ones are targeted more towards CPO and other higher density use cases.
Optimal for Intel is what meets the specs and can be volume manufactured on their own, proven 300mm sipho line.
It does seem though that this could be the end of the line for Si modulators.
200Gbps per lane is doable in conventional silicon photonics. Intel had a live demo on the floor at OFC; Marvell likely managed to do it as well, although unlike Intel they do not have their own sipho fab. Their 800G coherent pluggable is also sipho based.
No, EO material used is Silorix SOXD-224. The paper has some co-authors from KIT's organic chemistry department, whatever that may imply.
To be fair, there were more than 600 companies exhibiting. It's a reflection of the fact that one of the important themes at the conference was a much broader appreciation for the need to include novel materials to keep scaling. Whether LWLG takes the prize is very much TBD, but the visibility of this space was certainly elevated compared to earlier editions.
Jose also needs to keep it somewhat impartial and objective of course.
Double shoutout to LWLG in Jose Pozo's key take-aways from OFC
Making the optics faster can help in terms of reducing fiber count and/or wavelengths per fiber, but to scale aggregate end-to-end network capacity, the electronics need to scale along with the optics. Serdes, DAC/ADC, DSP, drivers, TIAs, all need to scale to the next data rate as well, otherwise the bottleneck just shifts elsewhere.
Maybe not the best analogy, but if you drop a much more powerful engine into a car, at some point you need to upgrade your transmission, brakes, fuel system, tires etc. to really get the power onto the road.
Valuable question! To a reasonable first approximation, the drive voltage is proportional to the half-wave voltage of the modulator (aka Vpi). Vpi (lower is better) in turn depends primarily on the following factors, assuming an MZM design:
- EO coefficient of the material (pm/V, bigger is better) and initial refractive index
- Electrode gap (smaller is better, up to a certain point)
- Length of the active region (longer is better in terms of Vpi)
- Wavelength (but this is not really a design parameter)
So even for the same material, you can make modulators with different values of Vpi, but there are trade-offs, e.g. a longer modulator generally has higher optical loss and lower bandwidth. So it could be either improved material with higher pm/V, or just a different design with the same material.
The authors of the SiPh roadmap paper, preeminent scientists in the field, were they "making things up" as well, is that what you are saying?
For reference (in case it hadn't been listed here), this is the survey paper in question, freely accessible: Roadmapping the next generation of silicon photonics. An illustrious author list, including Richard Soref, a founding father of silicon photonics.
Luckily I have parrothype on ignore
That is a wonderful paper and I highly recommend it to everyone, but can't lay claim to any of it
It may indeed require different assembly processes; not necessarily a show-stopper, but it eases adoption if one can play nicely with existing, well-established assembly processes.
260C is the right ballpark, probably not a coincidence? But would be good to have some headroom.
No, this has nothing to do with the PDK - this is after the PIC has been delivered to the customer.