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gb
Many thanks. Justin Rattners webcast served me for an update how Intel sees the world.
K.
wbmw
Idle power is really AMD's only advantage they have left, so it's no wonder that they are crowing over it so much.
In idle most juice used keeps the cache warm. Litte cache, little juice. Easy. But not for all, apparently.
K.
p.s.: If you want some spin on it: Maybe this is telling about what Brishane is really good for?
chipguy Tx for the update on this. K. <eom>
Chipguy
ATI's product development is highly tightly tuned to TSMC processes.
Heard AtI gives UMC a shot recently, though. Toolsets in foundries are not as different from each others it would look impossible from a manufacturing stance within a node.
On a broader look at it, what I thought would be the most compelling argument for a merger of AMD/AtI long before it happened was to allow adopting the model Intel uses and make chipsets and grafics in AMDs fabs after CPUs. But history rolled over this, as CS and grafics trend towards the leading-edge node nowadays.
As flash does as well, changes of Intels model are imminent down the road. I have not heard anything from Intel in this respect, did you?
K.
MiMic
could this take us back to the $40 days?? :))
Sure. And beyond, as well. If everyone buys it.
Or back to $3 or even below. If there is few that buy it.
Nice pic, btw.
K.
imho
Let's see what Intel does about this?
Nothing. Poor yields is just a common misperception. It's yields everybody has fabbing leading edge silicon, nowadays.
K.
imho
Hats off, mate. Never seen such a post from you. Needless to say, I second it. While I might add I don't believe you necessarily have to live the lie (although this is undisputedly the regular case). It's enough to tell it. Nietzsche was more precise on it - and able to put in one sentence what would take me an essay:
Who cannot lie, doth not know He what truth is.
Apologies I only have a translation to british language (from Thomas Common) at hand.
K.
Keith
Well while it would have been OT until recently, now Power Play is on thread. Do you remember AtI's Powerplay? Years back I fiddled around for quite a while to make it work on an ATI-product which was supposed to be capable of it. It never worked. Cough. Now they seem to have another name for it. Something Xpress or so. I hope this one works.
K.
p.s: I am aware i am violating board rule with it - i mean this is not even close to significant. Pls let me know if we should take it to somewhere else.
imho
Good hack, mate. Thanks. I assume you mean Rev 1.37 and 1.38, not
1.7 and 1.8?
K.
Keith
Failed to find the specs in the review. However, I just visited Dells German site. (I can't remember to have done that ever :) ).
Indeed the main battery is 85 WHrs. So that sounds different. And ist just over four hours with WLAN on. So i agree it does not need a second battery for this.
K.
Keith
Tx for the link. 5:30 for a 15,4" widescreen-book, i looked at specs and found they use a 53Whr battery. Sounds somewhat too good to be true. The runtime sounds rather for an operation with an optional second battery in the drive-bay.
K.
DURL
That's what I thought as well. Times when it was a no-no to even speak out AMDs name are just couple years ago.
K.
Lol. Wonder what comes out of it after the guilt digested it again. K.
wbmw
AMD expects the merger to be dilutive entering 2007 and accretive by the end of 2007."
Well AMDs explicit statement was "on path to accretion in 08".
Which made me a smile, for the two meanings of this term. I stumbled over it because it is not commonly used.
K.
wbmw
But that seems extreme, even for a cheerleader.
I do not remember any launch from Intel or AMD it did not happen. Only that fakers used to be brighter in former days.
On another note, I find it absolutely understandable a teenager reading all the reports bout Quad-FX and such from his Celeron- or Sempron-System easily creates enough envy to spend couple hours on his pirated Corelpaint or whatever to make him a hero for couple days.
K.
wbmw
That's why CPUZ calls it a rev-F, when a real Brisbane is a rev-G.
What I was getting at is CPU-Z of this revision does not know Brisbane by name, unless its revision history is incomplete.
For my part, I am not able to call a stranger by name when I first meet him before I read his card. You? :)
K.
mmoy
comments were more along the lines of what I've posted here.
Seconded.
SIMD programming is that writing an application for two cores is different from writing it for four cores. Sure, you can have two sets of code but your maintenance and support costs go up. If the hardware would just stabilize for a while, it might make for a more interesting target that software developers could work towards. And that's a similar problem with MMX, 3DNow, 3DNow Professional, SSE, SSE2, SSE3 and SSE4.
Yes. And beyond it. Cache hierarchy, for the matter. Which explains Barcelona's shared L3-cache.
Sad enough, AMD is not in a position allowing for a core-war for this very reason.
Bottom line, whatever BS-architecture Intel brings to the table, AMD has no choice than to make it so as well for the foreseeable future. I currently see nothing like IMC or 64-bit-extensions in its cards currently. Not surprizingly, Phil has "No core wars" in his charts today.
At times, pragmatic opportunism is the only viable strategy to survive.
K.
golfburn
i fully expect this to happen in early '07.
Well, yes, sure, I mean what does Knut Grimsrud know.... ;)
K.,
gb
Oh well. His wrapup is: "Short-term rocky- mid-term rosy - long term uncertain." Along with a long list of what needs to be done to make it mid-term rosy, naturally.
It did not make me a laugh, but a smile. It is what everybody does. "Treasure to raise - request budget" :)
Wrt mid-term rosy, while he has Disk-specs from today in his presentation, i could not find specs of the flash utilized in Forster-River (not sure i remember it right). But then, this again is what everyone does: Compare today's specs of technology A to tomorrows of technology B. It's just how things work. Knut knows his business and the rules of the game. Good.
And it is really as I stated before: Intels public presentations are rather conservative in this, relative to others. Hope Knut got his budget already.
K.
Comb
Tx for pm-comment@si. Helpful.
Shorthand-take on thread: 45nm? - yes. From beginning of node? - close to hopeless. Let alone 08. This decade? Possibly.
K.
gb
Many thanks for digging it up, mate. Scrolled through it. Good presentation, beyond just rah-rah.
pp 29ff - 43 is about what I was getting at. :)
K.
Alan
I am aware of some fairly old profile data that indicates the data is actually VERY static, and only a small portion is frequently updated.
If I were to dig into it, i probably would look at an analysis of the paging-file on disk to get a basic idea of it, in dimension.
Well, after updating on NAND and HD-specs, that is. ;)
Or more precisely, after making sure somebody is paying for it. :)
K.
gb
Hey, I am all for anything which delivers fun. However, this industry has a good tradition of blowing sand and is particularly good at it when it comes to memory. Not limited to Intel, naturally, they are rather careful with it relative to others, e.g. Innovative Silicon or the like. ;)
K.
gb
neither I dispute Grimsruds competence nor do I claim there is basically unsurmountable stopgap in the concept. If there is a lifetime-issue all you need to do is using manangement and as much reduncant flash as you reckon to need. Then it just comes down to a cost issue. If Flash is cheap enough, fine.
K.
Alan
Even at current flash speeds the improvement will be substantial.
This would surprise me. It is more than a year ago I looked at such configuration concepts, so maybe the spec-data are outdated. However, back then it did not come even close to a good disk.
Also, Intel had wear leveling in their very first flash file system from over ten years ago. I don't see this as a huge issue.
I agree. But it adds overhead. And it does probably not solve the lifetime-issue: The (admittedly a little old) data are in the 100K rewrites. Not an awful lot for such use.
K.
wmbw
It uses NAND flash technology from the Intel Micron joint venture.
I have no reason for any doubt on this. I am sure Micron has silicon of half a dozen candidates for future technologies in its labs. And lifetime considerations are irrelevant for running a demo.
K.
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deleted duplicate
Chipguy
Hmm. Robson requires future flash-technology. What is currently available in volume is too slow, no?
Feasibility of a "mezzanine memory" between system and disk will hinge on r/w-cycles of future flash specs, and on very sophisticated management of this memory as well, for lifetime considerations. Which adds middleware-overhead.
Suspend to flash is possible now, though. In a user-model where you use suspend-to-disk often (mine would be such one) it might save you some juice. 20 min extra would be an extreme, though. On a quick back of the envelope calc it would be in a model of 40 suspend-to-ram-cycles over course of a battery-cycle or so.
K.
Rink
See p.s. here: http://www.siliconinvestor.com/readmsg.aspx?msgid=23089770
K.
john
Been quite while since I looked at it. Still very helpful.
Highly appreciate your work - and Mike's, naturally.
I was touched when I learned your motivation for contest-hosting and maintaining your site is low currently. Gimme some time to catch up on things please. I do not want to throw a dart blindly currently - it probably would influence analysis. I'll do my very best to make it in time for making a fool out of me in the end-quarter contest again. :)
Hope for your understanding.
K.
p.s: Did you receive my email a while ago with updated adress?
p.p.s: Mike, prices mirror what I see in Europe. Or vice versa.
wmbw
It's nice to see an AMD investor...
Just to set the record straight: Not currently. Went long AMD when I saw a window of opportunity for them couple years back. Went out when I saw the window closing. Which was long before its recent spike - unfortunately .
To intersperse on-topic content: The next window of opportunity for AMD i can currently think of is many years away. I do not rule out to play the stock, but it would need to come down to single digits to consider this. This is as independent from my goodwill for the company as I can tell the two dimensions apart.
As it is an Intel-thread: It does not look attractive enough to consider it as an investment either, currently. The above remark on general attitude applies accordingly.
You may still get the occasional flame
We had our flame-tackles a while back, iirc ;), and still talk together. Nothing wrong with it, but evidence
1. we both are humans
2. we both accept we are.
K.
tecate
Well, boyz are to play, I said earlier today. But they are to fight as well. So they need places like this, I guess. Until they grow up, that is.
K.
ROFL
Gee, this seems to be a place for a good laugh now and then.
Kudos to tenchu for a comprehensive summary.
K.
elmer
Frankly, I thought you'd lack humor. I stand corrected. Good.
K.
wmbw
'bout as much as for shipping product of this node, i guess.
http://akiba.ascii24.com/akiba/news/2006/12/07/images/images827547.jpg
On a more serious note, it's interesting* to see an Intel thread working flawlessly w/o any moderation, while AMD-threads seem to have a tendency to be split into
-moderated
-strictly moderated
-off-topic
and whatever else subthreads.
Somewhat telling, I guess.
K.
* Edit: It's not only interesting to see. It feels good. So better make it it's good to see.
Many thanks, Alan.
Chipguy elaborated to me on another thread on it, but clearly indicated the effect would only be relevant well beyond 45nm, so there must be another reason. In particular in Layer one. :)
I was thinking it could have to do with the nasty damascene effects AMD has run into at its 130bulk node, that's why I asked if Intel has Al in its interconnects.
If you allow some spin for the fun of it, maybe Intel could avoid the problem finding a way to avoid one level of interconnect altogether. They are quite good at making things as good as they believe is enough - and this as cheap as possible. Occasionally they err on the former one, but barely on the latter one.
K.
alan
good to see you still around, to begin with.
Many thanks for retrieving data and posting it. As for your comments, PMOS/NMOS characteristics is just a part of the equation, insofar these data per se do not allow a compehensive assessment of the nodes. Pretty much d'accord with remainder of your comments.
From today's news, I see AMD/IBM is using Al for interconnect layer one in 45nm, and apparently in 65nm as well. Just curious, do you happen to know Intel does as well? And/or the reason for it?
On Litho, I do remember weakly Intel considered double exposure a long while ago, are they already doing so or said something about if they still have it in mind recently?
TIA
K.
p.s: Hi to everybody, in particular those I did not meet alread since i'm back.
Chipguy
That being said, AMD probably has other reasons to use an
Al layer at 65 nm because this scaling effect will likely only
really start to bite at perhaps 32 nm and below.
Right you are. These reasons seem to be good enough to use Al in 45nm as well:
http://journal.mycom.co.jp/articles/2006/12/12/iedm1/
The intermediate (middle level) and global (upper) wires will still be copper because of lower RC delay and much better
ability to carry high current reliably.
Apparently not. I see it is in layer 1. Just curious, do they do this in 90nm as well? I am asking because I remember they had nasty problems in 130 bulk with copper damascene effects, maybe that's why they use Al nowadays?
K.