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Alan, If Intel management tells their masses of engineers to focus on something else than what AMD management tells their engineers to focus on then it's still possible that AMD management made a better choice and as a result has a better manufacturing suit than Intel has despite the difference in engineers. Like with K8 vs. Prescott/Nocona, but now applied to automation of manufacturing process.
APM is reasonably widely published and recognized. My unknowns are more about Intel's automation efforts. I only know what has been available over the last decade or so in reasonably readable articles (I'm not a semicon or process automation engineer; I have only a very limited background in chip design so I understand some of the more basic concepts). UMC and Chartered think APM is a valuable asset. Copy Exactly might also be attractive if Intel would allow licensing but maybe for larger manufacturers like TSMC, UMC (there's no record of this though that I'm aware of); also Intel isn't touting Copy Exactly like they used to when they were further ahead of the rest. Gartner a couple of years back (2003?, start '04?) stated AMD leads in this area, and AMD hasn't been standing still. Sematech has recognized fab30 manufacturing as leading for (iirc) two years (haven't heard about this last year though). APM is patented by well over 200 patents (not copied from Intel as WBMW claims) and is being expanded at rapid pace with version 3 (I believe you mentioned that as well) ready for fab36 which will include Agent Based Scheduling among other things. I've seen a very large article claiming Intel isn't as far with APM as AMD is though I'm not sure at this point how much of the information was provided by AMD itself. I recall it said that Intel vastly out-influences tool makers (compared to AMD) and that that was the reason for AMD to try to out-implement Intel which eventually led to the APM suit. Probably 2 years old. Noone I know has usuable access to hard info like yields / bin splits for both companies, and ofcourse not for a more or less identical test subject.
re: What data I do have on this issue leads to me to believe Intel is quite a bit ahead in this area...
Anyway what data do you have to validate your assertion? I admit my data is limited; you might well know more.
Regards,
Rink
Re: One thing we can be certain of is that Intel has many, many more engineers working on this than AMD does. To believe that AMD has a better system is just wishful thinking.
True Intel has more engineers for everything. Also for cpu design. Boy did they mess up, particularly with their mainstream cpu line. Sure Intel has many more engineers working on aspects of process automation as well, but it's rather dense to think this by itself should suffice to exclude the possibility that Intel messed up once more(they're quite capable of that too).
Regards,
Rink
WBMW, what a display of ignorance.
re: You can't judge a process based on the features. If it were capable of such ultra-low power, why can't AMD get Turion down to the power levels of Pentium M
Yes, you can't judge a process EXCLUSIVELY on the features. You can't marginalize them either. Both a better quality of strain as well as SOI are recognized by the entire industry as beneficial for higher performance and/or lower power. Even by Intel though they say SOI is too costly for the advantages they saw themselves as well. Turion is of a K8 design created for servers first; Pentium M was designed for mobile ONLY. It e.g. has the ability to deactivate large portions of L2 cache in order to save on power consumption. That you even consider mentioning this as your only reason as to why Intel would have a better manufacturing process is REALLY beyond words.
Both Dothan, Prescott, Montecito had/will have lower introduction frequences than Intel led people to expect. You probably will play ignorant again I trust?
re: Ridiculous. APM is nothing more than AMD copying Intel's Copy Exactly methodology
LMAO!! APM is largely patented by well over 200 patents(meaning AMD was first to innovate, and meaning that Intel does not have legal access to that innovation). Copy Exactly is a fundamentally different from APM because the reason of their existance is different. Copy Exactly stems from Intel's need to have a process distributed as fast as possible over a multitude of fabs, APM stems from AMD's need to fully automate the whole production process (including all steps between different tools). AMD did first innovate in this area because it can't out-influence Intel with regards to tool manufacturers such as ASML and NEC (it could however out-implement Intel so that's where they focussed). AMD is in fact recognized by the industry (other fab companies e.g. UMC and Chartered, and industry analysts like Gartner, and the semiconductor manufacturing consortium Sematech) as taking this holistic approach to automating all process steps first and effectively. Fab36 will use the next major version of APM v3 that includes Agent Based Scheduling among other things (also patented for this purpose). Because I don't know enough about Intel process automation I can't be certain that APM is better than what Intel has but I think it is logical based on the information that I do have. In contrast with this you don't seem to know what you're talking about at all.
re: But I do have the correct knowledge to base my conclusions on. You just need to know the difference between design benefits and process benefits. Intel has the highest yielding, best performing process out there.
That's pretty presumptuous to claim 'correct knowledge' for your conclusions considering how little in fact you know. Yes K8 is a better design than comparable Intel designs. Still AMD's current process advantages like better strain, SOI, and probably APM are absolutely impossible to ignore as key components of better performing chips (in addition to the benefit coming from a better design). You have no factual basis for concluding that Intel's current manufacturing process is better than AMD's while I do to the contrary (I fully realize it's incomplete, but you have actually next to nothing).
I'm not going to bother with your other statements. Maybe someone else will.
Regards,
Rink
WBMW, re: Under any reasonable investment horizon [Intel is] a good buy.
You can't possibly be sure or objective. Remember you are only human. Remember how flawless the human logic can be. Now remember there are lots of other humans that are not completely in synch with your brain waves to the extent that some who are much more knowledgable than you are putting real money against your under all circumstances fail safe hypothesis (e.g. Fred Hickey).
Regards,
Rink
WBMW, re: Intel's process is and has been better.
Wrong. AMD currently has better strain than Intel. AMD has SOI. Intel's 65nm is nothing too special either (though it might get the quality of their strain up to current AMD/IBM levels). 45nm might allow Intel to gain the lead again better (high-k). Also, though it's not clear what Intel uses exactly there's a reasonable chance that AMD has an edge over Intel too with APM. Not that important but just maybe current advantages are part of the reason why AMD single core cpu's outperform Intel single cores don't you think (remember what leakage did to Prescott; remember rather 'hard' frequency ceilings for Banias and Dothan that prohibited scaling much past introduction frequencies)?
Historically you're wrong as well. Remember copper (.18) shortly after the start of the Athlon production?
If you really have no data or knowledge to base your above conclusion upon why bother to post it at all?
Regards,
Rink
CJ, agree. They're essential stop gap measures for Intel. Woodcrest due H2 '06 is a big part of the real solution they're hoping for. Woodcrest will still have mem latency and scalability disadvantages compared with the direct connect architecture. That problem will only be addressed H2 '07.
WBMW is ofcourse fully aware of that, which means that "Blackford and Dempsey will close the performance gap relative to DC Opteron" is an exaguration taken to an extreme (at best). It's crystal clear that no Netburst chip ever can. From another point of view however it's also clear that if Intel could not release these solutions a LOT more customers would jump ship.
Regards,
Rink
Tx (eom)
Buggi, re: playing field for Yonah/Sossaman
Predominantly mobile because as one of the design parameters for Yonah transistors was low power it can't scale like destop chip. Pentium M frequency ceiling has so far proved 'harder' than that of chips designed for desktop usage.
Yonah might have some limited success in low noise desktops requiring good mid-level dual core performance. How much is still a big question to me because it depends a lot more on how Intel will position it and not nearly as much on it's capabilities. My take is Intel will need to continue to produce a heck of a lot of Netburst desktops in order to keep enough top binning parts close to X2. Also I think Intel will not want to lower 64b share much. Lastly I think Intel might not want to risk lowering the image of single core Yonah which would happen if it choose to replace Netburst Celerons with it. My current wag therefore is that Yonah will carve out only a somewhat significant niche in the desktop market.
Sossaman will have rather limited success in blades because of 32b and because of Sossaman's short life span. Hopefully for Sossaman it just might be pin compatible with Woodcrest and have more or less the same power envellope; this would lower the barrier for blade designers to give it a go. I think Woodcrest will require more power however (like 70W vs. uhm 50W?; another wag; no solid info).
Couple of short bits:
- Exactly. Yonah will rather largely clearify performance of Merom/Conroe/Woodcrest.
- I'm not sure where all capacity will go. Lots of possibilities (the first of which with a somewhat low chance of happening H1 '06): Dragonfly, quad core, 3rd party chipsets, large volume 90nm DCs, larger share in volume markets, etc... As far as larger market share is concerned you're right that it'll have to come largely from desktop (SC and DC desktop lines will remain very strong till end '06). Considering how well Intel managed public perception of Pentium M (both current and future) Turion has some possibility to surprise (but Keith will have to be wrong about his implied late DC Turion intro date for that to happen).
- Intel's antitrust-OEM-rules won't be broken that significantly unless it's an absolute necessity for Intel. I think they'll only relax it marginally to keep up appearance of being reasonably non-abusive until close to the end of the lawsuit. Consequently I'm not sure with what AMD will fill fab30,36 and Chartered's fab7. Large question mark. Fab30 has to churn out valuable products all 2006 because it'll be depreciated only end '06.
- Oct 11 info will almost certainly contain some detail about chips it can currently produce, some info on depreciation, some info on the ramp probably incl planned shift to 65nm, etc..., all mostly for the sake of large investors. They'll undoubtedly feel that they need to put fab36 in a possitive light for all stakeholders.
EDIT: Just saw your reply to Rupert regarding possibilities for more AMD cpu volume. Fully agree.
Regards,
Rink
Buggi, re: but it seems to me, that these actions are normal in Intel-operation modus (last year).
But.. but... Intel promised to do better and be very conservative for it's roadmaps as of a year ago!!
To be honest their roadmap for Pentium M derivatives looks pretty solid so far. Their performance projections for these look slightly fishy to me. I can't exactly put my finger on it (so I could be well wrong about this). In order to be sure one way or another I still would like to see Yonah benches on real applications.
About the real power envellopes: Very nice find! Yesterday when I posted about them on SI I was only able to remark that I found it nice to see Intel is now using approx. the same power envellopes as Opteron for their lower power single core chips, i.e. 55W and 90W (or really 60W and 97W when using the same rules as AMD and the rest of the industry uses). Still quite close to normal DC Opteron and DC Opteron HE. http://www.siliconinvestor.com/readmsg.aspx?msgid=21740002
re: The 110W parts are 120W ... and so on. Thats the way Intel played all the years but didn't show in the SPEC files. They changed, wondering why?
Have you seen that full screen data center melt down add by AMD yesterday? After full screen show it shrinks to the right hand side of the screen here: http://news.com.com/
Also the lower power versions are single core only for as far as I've seen. Dual Core Netburst will probably require two of these 'very low' power 55W (alias 60W) cores. The SC 55W parts are supposed to become available at 3.0GHz. Paxville at 2.8GHz. It all fits nicely.
Regards,
Rink
Buggi, yes, can't count the times Chipguy was wrong about Itanium performance estimates. Should remind all of us not to get attached too much to anything not important.
Regards,
Rink
Montecito, Montvale beset by very hard times
http://www.theinquirer.net/?article=26519
Montecito will at least be of C1 stepping once it comes out early Feb '06. It says that because C0 is pretty much full of bugs it's not sure if the C1 stepping will suffice for launch in which case Montecito will require a D stepping (which would then cause further delay). Foxton might not make final release either. They write there's even a good chance that the frequency of the pare might never exceed 2.0 GHz. Lot of vague statements, but the statement about C1 looks solid enough to me.
Alan, If true this means more than 2 complete mask sets to get there which means costs per unit are higher than expected.
Regards,
Rink
Alan, tx for the info (eom)
Alan,
Mask set costs. I think you estimate them too low for two reasons. The smaller is that I think the price of 90nm 300mm mask sets are higher than you state. More importantly however I think it takes more mask sets than 2 to get from tape out to production, while even during production changes are made e.g. to some of the masks. It's not my field however. I can easily be wrong. It's from what I remember reading (anywhere from $600K-1.5M per set iirc). How much do you know about this?
re: I tried to answer the question: "would Intel financials this quarter, next quarter, and next year be better or worse off if Intel decided to ax Itanium."
I understand that now (after having read back the thread as a whole). Just don't call it 'Itanium profitability' next time please because that's something else; you had me going the wrong way.
re: sharing of infrastructure... You're right they're not doing real development on current Itanium chipsets. They'll at least need some development (partly shared with x86) for CSI chipsets for Itanium H2 '06. That development must be happening around now. You see, I think that Itanium chipsets won't be 100% the same as x86 chipsets (features?, bandwidth?, etc... chances are it will not be exactly the same). If they are you are more right, it will still need verification at all stages.
re: Silicon process development costs... You could be right; I really think however there's costs involved for verifying validating etc... the process for 600mm^2 Montecito dies. This needs to be done before you create a design that needs such a big die. Plus that cost is not directly shared with any 90nm x86 processor. There might very well be more cost items. I'm not an expert. I can only express that it makes some generic sense to me.
re: Software development costs... re: I would certainly expect Intel to stop spending money here before they EOL the product Intel would have mentioned stopping sponsoring Itanium software development. They haven't. I think they need to continue to sponsor all non specific big tin software or loose out even more against x86.
re: Marketing... I think you're wildly mistaken. Marketing costs per unit might well be way higher for Itanium than they have ever been for any x86 chip. The Itanium brand is marketed. I've seen adds reasonably regularly. There's the strategic deals that Itanium spends more on per unit than x86. The brand would definitely loose much more weight if it wasn't for marketing. Marketing costs at Intel are considerable. It's very un-Intel not to continue to spend good money on Itanium marketing.
Regards,
Rink
Joe, yeah you're right. Woggut, m'excuse for taking your comments a step too far (with regards to asking to address the other points as well). I fully understand your general point. However when talking about 'Itanium profitability' (as in Alan's post) one should include all costs made to create and market it. Operational profit is something else. Return on future investment still another. 'nough said about this bit.
EDIT: Reading further back in the thread the original subject was more about Op profit and return on new investment. I was mistaken to interpret Alan's mention of 'Itanium profitability' literally. Still most of the comments I made are not less valid now.
Regards,
Rink
Woggut, duh!!
We were talking about 'Itanium profitability'. The mere fact that the development costs are in the books means they have to be counted. 'Itanium' simply cannot be profitable unless all costs made to create and market it are covered. Maybe you want to be talking about Madison (or expected Montecito/Montvale) profitability instead?
Considering that for a moment, you didn't address any of the other points.
Regards,
Rink
Alan, re: Itanium profitability.
Some questions:
- Do you know what test wafers / new mask sets cost, and how much are necessary over the life time of a particular chip (like Madison, or Montecito? Mask sets for 300mm 90nm are quite expensive. They become real costs when resulting wafer volume is low. Maybe you have, but I don't see how you considered this and other one time costs.
- Why do you only try to estimate current development costs when forming an opinion about 'Itanium profitability'? Shouldn't all dev costs so far be included when discussing this? You can't just discard it like it never happened.
- I think that Itanium CAN'T share x86 server boards or much of the infrastructure at all until CSI which is currently scheduled for H2 '07. So why talk like this is already the case? Itanium e.g. uses twice the FSB size as current x86, uses a different memory controller, different board layouts, etc...
- Silicon process development is ALSO done for Itanium and therefore it doesn't make any sense to exclude it. There is even likely to be specific Itanium related process development, e.g. related to large 600mm^2 dies.
- Ofcourse Intel is still also paying developers to work on Itanium software, albeit maybe not as much as in earlier stages.
- Then there's marketing costs. If you talk 'Itanium profitability' those count too (and not only what is currently spend on marketing).
Just some thoughts.
Regards,
Rink
Oh, that's ofcourse why I had 802.11b far before Centrino ever existed (wireless router + pcmcia for several notebooks). And I was the only one smart enough to predict the standard a year before Centrino. I must be REALLY smart :)
Intel adopted THE standard, after that standard established itself as such in the marketplace.
And BTW my pcmcia solution from back then interacts just fine with Centrino hotspots that only emerged years later. How the heck is that possible if Intel 'solved the interoperability problems'? I'm still using it now and then.
The widespread INTEGRATION of WiFi was FOR A BIG PART driven by the Centrino platform. That's all Intel did. Intel put its volume behind the established standard making it an even more solid standard. Centrino speeded up adoption rate of 802.11b, and made hot spots far more plentiful than we'd otherwise would have seen. What it didn't do is establishing 802.11b (now g) as the industry standard. It was in fact so far behind that it had to license Philips hardware for their complete wireless solution. All in all Intel's contribution to adoption of 802.11b was still very sizeable.
Regards,
Rink
Buggi, I trust you factored in higher depreciation as a result of start of fab36 while fab30 isn't fully depreciated until end 06?
For me this is quite a big question mark. Depreciation and Amortization was +- $1B in 2003, and $1.2B in 2004. Those are large numbers that can impact 2006 earnings. They might reach $2B in 2006???, and then fall back to a bit over $1B in 2007 (as fab30 will be fully depreciated then).
AMD will not have a miracle solution to keep all fab capacity utilized in 2006. There's fab30 that doesn't need to be converted (full capacity available). There's fab36 ramping up (90nm converting to 65nm). Then there's Chartered fab7(?) which is largely flex capacity iirc.
There are a lot of possibilities for additional volume demand for AMDs products but most have a relative low chance of succeeding:
- high volume 90nm DC processors (this possibility has actually a reasonably high chance of happening)
- nVidia chipsets
- Rising Geode volumes (DragonFly)
- Dell/Sony and the like (low chance. The lawsuit isn't going to be finished in 2006 and they seem to LOVE Intels cocaine which will in fact be legal until ruled illegal.)
- Rising Sempron volumes in 2007 (65nm single core K8 might be quite attractive for India/China).
So unless some major OEM's are going to use AMD processors in their volume lines demand for AMD products does not seem to be able to match fast rising AMD fab capacity.
Regards,
Rink
Buggi, re: Our price target for AMD is $20. Our primary valuation methodology is an average of price to earnings and price to sales, with these multiples derived from weekly samples over a trailing five-year period. Both of these metrics are traditionally well-correlated to semiconductor stocks in periods of growth.
Our $20 target price is based upon a 39.7x multiple of estimated 2006 earnings per share of $0.56. The 39.7x multiple is equal to the five year historical forward earnings multiple. Our target price derived from historical P/E is $22.24.
As a second valuation methodology, our $20 target price is based upon a 1.4x multiple of estimated 2006 sales per share of $13.29. The 1.4x multiple is equal to the five-year historical price to sales ratio and results in a target price of $18.41
Note that SSB does not put any value on revenue growth, OM growth, and market share growth (their multiples of 39.7 and 1.4 do not change if AMD is set to grow permanently from current base). Isn't that a bit weird?
Regards,
Rink
(deleted; duplicate)
Tx (eom)
Wbmw, I have mentioned a reason, and have mentioned I am not sure what it's going to be like. BTW I was posting those up till 3 AM my morning when I said I'd quit for that day and have been away for the weekend (so hold your horses).
Reasons:
1. I've seen it mentioned in an article. Four months ago I think. No I haven't stored a link, and searching for it for 5 minutes didn't bring the article back.
2. Vastly reducing the activity of one of the cores makes sense when operated in mobile mode because it takes less power and for the majority of the applications that are on the market and are single thread a second core does not provide much additional performance.
I have given above reasons twice before, but maybe you can't believe I'd rather stick to those than take your word for it. I just very much doubt you know, right? There are a couple of persons on this board whose analysis or knowledge I'd believe fairly immediately as they've proved themselves to me before. The reason you provide, namely the fact that Intel has a "elegant power management scheme" is not exactly telling enough. The nice Anand article that you provided mentioned specific power management states but did not mention what invokes those states.
That's why I said three or four times now let's just wait and see.
Hope you provide new arguments. If not this is my last post on the subject.
Regards,
Rink
JM, re: then intel must be pretty stupid for spending so much time on their SmartCache technology .
JM, Intel's SmartCache just means that cache will consume even less average power on L2 when compared to transistors used for the core. Hence my remark that Twice as much as transistors for the cores - L2 transistors aren't nearly as leaky as transistors used for logic; [leakage of] L2 transistors doesn't matter nearly as much [as leakage of core transistors]. is even more valid.
Regards,
Rink
Alan, re: For 65nm Intel has not reduced gate oxide thickness.
Thanks. This will indeed infuence leakage.
About the amount of cores operating in mobile mode, let's just wait and see.
Regards,
Rink
JM, Twice as much as transistors for the cores. L2 transistors aren't nearly as leaky as transistors used for logic; they do not matter nearly as much.
Regards,
Rink
Wbmw, I'm not going to bother (because I've done that already + I'm done for today). You will have to wait and see (just like me).
Regards,
Rink
Wbmw, first thanks for changing your previously rather strong language.
That Anand article from March contains power states of Yonah, but does not state what initiates those states. The fact that you mention this article as counter argument plus the fact that you so far did not mention a single logical reason why Yonah would not operate virtually exclusively on one core while not plugged in leads me to believe that you have no basis for your remarks. This does not mean you are wrong about normal dual core operation when not plugged in; it just means I think it's unlikely for the reasons I mentioned in my previous post to you.
Let me go into one detail that seems important for you. Apparently Mooly at this at Spring IDF did say: "Yonah battery life will not be shorter than Dothan battery life ... a huge achievement". First, this guy knows who best to pat on the back. More importantly however TDP of Yonah is in fact higher than Dothan (by 20-50% as I've stated before) hence battery life under full performance is almost certainly lower (which btw pretty much invalidates the entire quote). Also notice that the quote doesn't say under which circumstances Yonah's battery life will not be shorter than Dothans. Then figure out that both doubling the transistors as well as going to a new node is rather likely to increase leakage when comparing at max frequency for 90nm Dothan and 65nm Yonah. Please don't tell me Intel always is straight about the truth, or that we should always believe them at face value. Lastly March Anand was rather unlikely to be able to verify this by any sample benchmark either.
If you only have this single out-of-context quote why on earth tell me flat out that it's "B.S." and "FUD" without providing any reason why?
Anyways, I can't but suggest again we'll have to wait and see.
To be complete so you don't get me wrong: I think that Yonah will be the highest performing T&L notebook chip for quite a while.
Regards,
Rink
Wbmw, if you want to be so accusive in your language why don't you provide a few links, or other facts?
Yonah TDP is higher than the normal voltage Dothans. 31W is more than 21-27W*, isn't it? In fact it's ~18 to 50% higher. So why accuse me of saying this is B.S.?? It's simply a fact. FWIW Banias was something like 24.5W IIRC.
And doesn't it make common sense to stop operating one core in mobile operation especially if it's not needed (it will only consume more power if you let it stay active). Mobile cpu's nowadays downclock during mobile operation when max performance is not needed. Plus this is in fact what I read will happen. Not sure though if it's really true, but I rather believe what I read until someone I trust shows me differently. So let's just wait and see who's right here, unless you provide some evidence of that rather strong language you are using. Why do you use that kind of language btw?
re: Yonah is a 65nm product with new leakage improvements, so both cores could in fact have less idle dissipation than a single core. We'll have to wait for tests to confirm this, but Intel's comments suggest that it will at least be comparable idly with Dothan.
Yonah is a 65nm product with twice the amount of opportunities to leak (as it has about twice as much transistors). Whether or not that leakage shows at idling and/or near idling and/or full operation is of no importance to me. I believe however that for the reason I mentioned that leakage can only exceed that of Dothan in all those situations. It just can't be completely concealed only by more advanced strain. I believe that to be impossible because it does not make sense to me. Also it's the general trend (more leakage with every new generation). If you believe differently please do give me a single logical reason why, if you can that is. Plus I don't give a hoot about Intel's comments unless I can interpret them myself directly.
Regards,
Rink
*21W for Dothan with 400MHz FSB, 27MHz for Dothan with 533MHz FSB.
wbmw, re: Except that everything Intel has been saying about Yonah is that it will offer equal battery life and form factors as Dothan, but with the availability of dual core for free.
That is because in mobile operation only one of the cores will be active while still having the availability of all L2 when needed. It's a good concept.
If however double core functionality would be forced when not plugged in to the net Yonah will have lower battery life as its TDP is in fact higher, plus two cores idling will rather likely consume more power two than current single core.
Regards,
Rink
Keith, re: the question is when AMD will be able to deliver a DC mobile part on 65nm. Before 2007? I highly doubt that.
Why? AMD has a HE DC Opteron already now on 90nm. What makes you think a 65nm DC Turion ML is out of the question Q4 '06? If history is any guide AMD will introduce mobile products first on 65nm, so why not a 65nm DC Turion in Q4? Do you think perhaps that AMD will delay 65nm production beyond Q3 '06?
Regards,
Rink
What next generation? 90nm rev F / 65nm K8 / or K10?
Regards,
Rink
Klaus, the short answer is that 4 bits per cell is not possible for NAND because it would require 16 voltage levels (/charges). 4 voltage levels will be the maximum for quite a while (or more precisely: 16 voltage levels per cell won't become possible for quite a while, neither for NAND nor for NOR architectures).
4 bits per cell is also not possible for any current NOR architecture other than MLC on Mirrorbit (/NROM/TwinBit/whatever else it is called). Consequently Intel will not go 4 bits per cell for a long while. Intel is working on something else (what is unclear) but it is nearly certain that that something else won't become available for a couple of years.
The reason why it is possible for MLC on Mirrorbit (QuadBit) is that a Mirrorbit cell has two physically separate storage locations. Each of these locations will contain 4 levels of charges (4 different voltages). This gives 4*4=16 states per cell, or 4 bits per cell, with only 4 different voltage levels.
Spansion has a good chance of becoming increasingly profitable for a year or two as of now. (Mind you, I was wrong about Mirrorbit adoption rate when it was first introduced, so take this for what you think it's worth.)
Regards,
Rink
Joe, I've seen information too that QuadBit will be implemented as MLC on Mirrorbit: 2 physically seperated storage places per cell with each four charges in them, totalling 16 different states or 4 bits per cell.
Couldn't find the link anymore.
Regards,
Rink
Doug, exactly how I recall it as well. I remember however thinking at the time that the end of that phase-in period you mentioned might be Dec 2005, but it does start to look like that period might be somewhat longer than what I was thinking back then (when it became clear that Galaxy be released on phases; I think about a quarter ago). No hard info yet on the release date of especially the 8 socket Galaxy server, not that I know of that is.
Regards,
Rink
Chipguy, that is hardly relevant. Alpha revenue didn't support R&D for most of its life, while both ARM rev and x86 rev are more than large enough to sustain them.
Regards,
Rink
Keith, burn baby burn!! ... Klaus, your post about SGIs Montecito sell in Germany says that a unified memory space for this 750 processor system was key. I take it that a unified memory space currently isn't practical for AMD systems larger than 8 processors???
Regards,
Rink
Tx. I crossposted your post over at SI btw (eom)
What does the 'T' in 'OpteronT' mean?
Impressive Montecito sell that one (eom)
Wbmw, I never heard AMD say 'early 2006' for 65nm. H1 06 is what I heard (meaning end H1). Link?
Regards,
Rink