Advanced Micro Devices Inc (AMD)

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Klaus, the short answer is that 4 bits per cell is not possible for NAND because it would require 16 voltage levels (/charges). 4 voltage levels will be the maximum for quite a while (or more precisely: 16 voltage levels per cell won't become possible for quite a while, neither for NAND nor for NOR architectures).

4 bits per cell is also not possible for any current NOR architecture other than MLC on Mirrorbit (/NROM/TwinBit/whatever else it is called). Consequently Intel will not go 4 bits per cell for a long while. Intel is working on something else (what is unclear) but it is nearly certain that that something else won't become available for a couple of years.

The reason why it is possible for MLC on Mirrorbit (QuadBit) is that a Mirrorbit cell has two physically separate storage locations. Each of these locations will contain 4 levels of charges (4 different voltages). This gives 4*4=16 states per cell, or 4 bits per cell, with only 4 different voltage levels.

Spansion has a good chance of becoming increasingly profitable for a year or two as of now. (Mind you, I was wrong about Mirrorbit adoption rate when it was first introduced, so take this for what you think it's worth.)

Regards,

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