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Replies to post #46088 on Intel Corp (INTC)

Replies to #46088 on Intel Corp (INTC)

chipguy

07/24/07 11:03 PM

#46090 RE: poweree #46088

Halt state does not mean that processor is completly halted and that all power draw comes from leakage. This is not true, because the clock is still switching, caches are updated, memory interface is working, interrupts controlled, etc. Only the pipeline stops execution (gated).

Instruction fetch and execution represent the vast majority
of dynamic power consumption in the processor. Yet even in
full out execution leakage power represents a considerable
portion of power consumption at 65 nm, approximately one
third. In halt state the majority of power will be from leakage.
The fact that there is a minor dynamic component from the
PLL, HTT snooping etc, doesn't materially change wbmw's
conjectures.

The reason why AMD delivers always the lower speed grades with their latest process is also quite simple: manufactoring costs. Die size of 65 nm parts is lower and therefore production cost is lower.

That's BS. Historically new x86 process nodes are used
to produce the highest value products (mobile, enthusiast
desktop etc) because volumes during ramping are limited,
yield isn't yet mature, cost per unit wafer area is much
higher initially, and performance/power benefits for ASPs
are the highest.

The fact that AMD introduced slower parts in their last
few new processes is straight out deficiency in delivering
steppings with fully wrung speed paths early enough to
exceed the mature steppings of the previous process. This
is likely due to limited resources and a rush to market
from competitive pressures from always being behind Intel
in process.

And regarding IBM, just look on their 4,7 GHz power 6 so process is really a no brainer.

A boutique server RISC processor burning over 150 W is
the slightest bit relevent to commodity x86 products made
by a different company in a different fab and likely with
significant differences in process, in what way?

Also SOI reduces leakage, because leakage through die is removed because of silicon on isolator (SOI) isolating such leakage (exactly what the name SOI stands for)!

If you had the slightest clue what you were talking about
you wouldn't have bothered to dredge up this old canard.
The active region junction leakage that SOI suppresses
is insignificant at 65 nm compared to the gate tunneling
and subthreshold leakage common to both bulk and SOI
CMOS processes.

Regarding low initial announced clock rates of Barcelona CPUs: AMD has SpeedPath issues. That means they need some mask revision to increase clock speed (with removed speed pathes) but no changes on process.

Barcelona appears to have many issues at the present and
craptastic path tuning is probably one of them. But that
likely proposition in no way suggests there are no other
issues with AMD's 65 nm process that needs fixing. The
fact that AMD's 65 nm K8s are still so far behind their
90 nm ancestors in delivered frequency strongly suggests
there is.






wbmw

07/25/07 3:03 AM

#46093 RE: poweree #46088

Poweree, I appreciate you responding to add to this discussion. I will try to address at least a few of your points.

Re: Therefore the posted comparison is incorrect. Correct comparison is:

Perhaps you misunderstand the point of the analysis. I was not comparing point products; although, you seem to have an idea of the positioning of certain products from a marketing point of view. My analysis was actually created to show process variation across the *entire* 90nm and 65nm process lines. In order to do that, I attempted to sample both high leakage and low leakage skus from both process nodes. My observation is that AMD tends to use the highest leakage parts as their lower frequency downbins, and likewise uses their low leakage parts for their highest frequency bins. This should not be surprising in an environment that is mostly thermally limited. And my findings showed that AMD's 65nm process, while lower power at the low end, also had a much wider variation than their more mature 90nm process. And it just so happens that process variation at smaller and smaller nodes can lead to very high leakage parts being created, that either need to be binned as very low voltage, low frequency downbins, or thrown away altogether.

Re: So the 65 nm parts are better in overall power envelope (TDP) and have a significant lower leakage.

Your two disconnected sample points hardly prove that. My sample size included the two that you used, as well as many more.

Re: However if you compare 90 nm special TDP selected parts to 65 nm standard (unselected) parts you come to such a completly wrong conclusion.

I would hope that any conclusion you make involves a sample size of more than two parts. You are free to broaden the sample size, but your definition of "special TDP selected parts" is debatable, at best. The 90nm 65W parts were quite common, up until just recently.

Re: Halt state does not mean that processor is completly halted and that all power draw comes from leakage. This is not true, because the clock is still switching, caches are updated, memory interface is working, interrupts controlled, etc. Only the pipeline stops execution (gated).

It's a close enough approximation, because dynamic power in C1 state is very low. If it were anything other than insignificant, you would get a visible increase in C1 @ max P-state current draw with higher frequency parts (because dynamic power scales linearly with frequency); but in fact you get lower C1 current draw, because the leakage is lower, because AMD bins them that way due to thermals.

Re: So even if static leakage of 65 nm parts is a bit more than of the 90 nm selected parts, the dynamic power draw is less and thus allowing higher clock speeds at same TDP envelope.

I would expect lower dynamic power. I never disputed that. However, AMD has yet to release a higher clocked 65W part on 65nm than they have currently released already at 90nm. The highest 65W parts are 2.6GHz in both cases.

Re: Even more as you see on page 12 table 1, the 65 nm parts have a new revision (G1) which indicates a mask revision. With that different clock gating / etc. could have been established in this revision making it impossible to compare power draw in anything but with full load (to get indications on process).

Actually, it appears that *all* 65nm parts to this date have used the G1 stepping. The commonly accepted belief today is that AMD made rather minor tweaks to their Windsor design in order to derive the current Brisbane. If this were not so, then transistor counts might be substantially off, and there could be major changes to the way that the power management modes operate. However, I have made the assumption that any changes in transistor count and power management architecture have been rather minor, and many comparisons of Brisbane with respect to Windsor support this presumption. If you have data showing otherwise, I would appreciate seeing it.

Re: As you see with the Intel numbers you can see how much a mask revision has impact on these numbers: Intel increased clock gating on the E6x20 series and thus lowered halt current draw by factor 2.5 on the same process.

Actually, I suspect Intel lowered current draw on their various Core 2 steppings by allowing further voltage reductions. Given that leakage varies strongly with voltage, you can get a sizable savings with just a hundred millivolts or so of reduction. Conversely, AMD's datasheet has shown the voltages for their 90nm and 65nm parts, both at max P-state and min P-state, and I displayed those prominently in my analysis.

Re: In addition if you read power draw tests of AMD Athlon X2 CPUs you see that 65 nm have lower power draw than 90 nm under all conditions. The 65 nm standard parts can even compete with the SFF ultra low power parts.

Again, the results in anything other than C1 state was irrelevant to my analysis, so I didn't spend much time looking into them. On the other hand, if AMD could have competed with 65nm standard parts in SFF ultra low power systems, then they wouldn't have needed to launch their BE-2000 series of 45W TDP parts. It seems to me that some of their new chips are binning better in terms of leakage, and I would have included these in my analysis, had AMD published the specs in their datasheet.

Re: The reason why AMD delivers always the lower speed grades with their latest process is also quite simple: manufactoring costs. Die size of 65 nm parts is lower and therefore production cost is lower (in addition the 65 nm fab uses 300 mm wafer compared to 90 nm/200 mm Fab30). So they use them for the less expensive lower speed grades.

This is a senseless argument to be made 7 months after the beginning of the 65nm transition, and after they have claimed a complete transition of their fab36. By now, they would have introduced high end parts in addition to their low end cost saving parts, and perhaps saved a bit of their rapidly decreasing desktop ASPs. Unfortunately, nothing above 2.6GHz has yet to launch on 65nm.

Re: And regarding IBM, just look on their 4,7 GHz power 6 so process is really a no brainer.

This seems to be a complete non-sequitor to this discussion. Not only are there many doubts as to how close the AMD and IBM processes actually are, but the Power 6 is also a very high wattage part with a fairly large ratio of leakage in it. Its simplified pipeline and frequency driven design might have enabled 4.7GHz, but one does not presume that this gives AMD's 65nm process any special ability of delivering the same to AMD's 65nm designs.

Re: The real problem was, that AMD is always a bit late in establishing processes because SOI/SiGe support takes longer than Intels plain Si-Process (and maybe can make less investments in fabs than Intel). However the SOI process has of course more potential than the plain one.

AMD's process design choices have real market impact. Just look at their 3 most recent quarters in terms of YoY revenues and losses, and you'll see what I mean.

Re: Regarding low initial announced clock rates of Barcelona CPUs: AMD has SpeedPath issues. That means they need some mask revision to increase clock speed (with removed speed pathes) but no changes on process.

You seem to be grossly oversimplifying AMD's problem set with Barcelona. Already, AMD's partners are confessing about problems with voltages and high power levels (#msg-21526853), which ironically supports the POV of my analysis. Secondly, the design is late, slow, and not sampling in sufficient quantities, even to support a September launch. My theory on this is that the problem is more fundamental than just a series of speedpath issues, and may more likely be the result of process variation and leakage problems.

Snowrider2

07/25/07 10:17 AM

#46096 RE: poweree #46088

poweree,

This is the first time I've seen you post on this board. In fact, the record shows you've only posted twice. Pure speculation and probably wrong, but I think you're probably an AMD PR Rep. Guess WBMW's post being captured in a tech journal caught more than the investors on this board's attention.

Snow