Halt state does not mean that processor is completly halted and that all power draw comes from leakage. This is not true, because the clock is still switching, caches are updated, memory interface is working, interrupts controlled, etc. Only the pipeline stops execution (gated).
Instruction fetch and execution represent the vast majority
of dynamic power consumption in the processor. Yet even in
full out execution leakage power represents a considerable
portion of power consumption at 65 nm, approximately one
third. In halt state the majority of power will be from leakage.
The fact that there is a minor dynamic component from the
PLL, HTT snooping etc, doesn't materially change wbmw's
conjectures.
The reason why AMD delivers always the lower speed grades with their latest process is also quite simple: manufactoring costs. Die size of 65 nm parts is lower and therefore production cost is lower.
That's BS. Historically new x86 process nodes are used
to produce the highest value products (mobile, enthusiast
desktop etc) because volumes during ramping are limited,
yield isn't yet mature, cost per unit wafer area is much
higher initially, and performance/power benefits for ASPs
are the highest.
The fact that AMD introduced slower parts in their last
few new processes is straight out deficiency in delivering
steppings with fully wrung speed paths early enough to
exceed the mature steppings of the previous process. This
is likely due to limited resources and a rush to market
from competitive pressures from always being behind Intel
in process.
And regarding IBM, just look on their 4,7 GHz power 6 so process is really a no brainer.
A boutique server RISC processor burning over 150 W is
the slightest bit relevent to commodity x86 products made
by a different company in a different fab and likely with
significant differences in process, in what way?
Also SOI reduces leakage, because leakage through die is removed because of silicon on isolator (SOI) isolating such leakage (exactly what the name SOI stands for)!
If you had the slightest clue what you were talking about
you wouldn't have bothered to dredge up this old canard.
The active region junction leakage that SOI suppresses
is insignificant at 65 nm compared to the gate tunneling
and subthreshold leakage common to both bulk and SOI
CMOS processes.
Regarding low initial announced clock rates of Barcelona CPUs: AMD has SpeedPath issues. That means they need some mask revision to increase clock speed (with removed speed pathes) but no changes on process.
Barcelona appears to have many issues at the present and
craptastic path tuning is probably one of them. But that
likely proposition in no way suggests there are no other
issues with AMD's 65 nm process that needs fixing. The
fact that AMD's 65 nm K8s are still so far behind their
90 nm ancestors in delivered frequency strongly suggests
there is.
AI
