Replies to post #131168 on Intel Corp (INTC)

[RobertG]

Xilinx Starts Unveiling 16nm UltraScale MPSoC Architecture


Max Maxfield
3/6/2014 04:25 PM EST

I just got off the phone with Steve Glaser, senior vice president of corporate strategy and marketing for Xilinx. He very kindly brought me up to date on his company's forthcoming UltraScale MPSoC devices, which will be introduced at the 16nm technology node.

Actually, this can all be a tad confusing, so let's take a moment to set the scene. When Xilinx adopted the 28nm technology node, it released its lowest-power, smallest-form-factor Artix; its best price-and-performance per watt Kintex; and its high-capacity, high-bandwidth Virtex families at this node. It also released its Zynq All Programmable SoC devices at the 28nm node.

The current All Programmable SoC at the 28nm technology node, the Zynq, is hardware, software, and I/O programmable. It boasts a homogenous dual-core ARM Cortex-A9 microcontroller subsystem (running at up to 1 GHz and including floating-point engines, on-chip cache, counters, timers, etc.), coupled with a wide range of hard-core interface functions (SPI, I2C, CAN, etc.) and a hard core dynamic memory controller. All this is augmented by a large quantity of traditional programmable fabric and a substantial number of general-purpose input/output pins.

When we come to the 20nm technology node, only the Kintex and Virtex families are being brought forward with the UltraScale architecture. The Artix family will hold the fort at the 28nm node. When we say UltraScale, we're talking about a radical new FPGA architecture that offers massive -- ASIC-class -- I/O bandwidth, memory bandwidth, and DSP processing capabilities. In the case of the programmable fabric, we're talking about millions of logic cells all supported by ASIC-class data-flow and routing resources.


The first 20nm UltraScale devices started shipping in December, but Xilinx is already looking to the 16nm future. In addition to UltraScale FPGAs and 3D ICs, the company will field a family of 16nm multi-processor SoCs (MPSoCs). In addition to UltraScale FPGA fabric, these devices will boast a heterogeneous multicore processing capability...
http://www.eetimes.com/document.asp?doc_id=1321334&;

[RobertG]

16nm Pushes Chip Design Boundaries at CDNLive

Nick Flaherty
3/7/2014 09:45 AM EST

TSMC’s 16nm FinFet technology is making its way out in to the world to offer even more transistors to use. The ramifications for FinFet, as well as several other issues related to chip design, are just of the subjects that are expected to be discussed and debated at the CDNLive conference, which starts March 11 at the Santa Clara Convention Center in Santa Clara, Calif.

In his talk, Bob Mullen, technical manager for Design Methodology and Design Technology Platform for TSMC, is expected to detail information about the custom design reference flow and all the elements that make this a front-to-back flow. At the same time, another FinFet user, Intel, is tackling the complexities of designing at this node.

Laurent Isenegger, a senior system modelling engineer at Intel, is showing how linking his company’s CoFLuent Studio software with Cadence’s C-to-Silicon tool works across multiple consistent hierarchies to speed development with a high-level design approach. Low power is also another key theme that is increasingly important in a high-level design methodology with the latest process technologies.

Mark Warren a field group director at Cadence is looking at how high-level synthesis can help reduce power, while Leah Clark, an associate technical director at Broadcom, is looking at how CLP helps deliver full chip static power verification for the chips that will be using these leading-edge process technologies.

ARM’s Raviraj Mahatme is also looking at the innovations in low power design for the Cortex-A53 processor, the “little” core in a big.LITTLE implementation. Other keynote speakers for the conference include Lip-Bu Tan, president and CEO at Cadence; Krishna Yarlagadda, US president of MIPS CPU core developer and the POwerVR graphics developer for ImaginationTechnologies; and Chris Rowen, founder of Tensilica and now a Cadence Fellow.

In addition, Cisco Systems, Hewlett Packard, Samsung Microchip, and Freescale Semiconductor will have engineers on site to talk about the challenges facing their chip designs, as well as the issues of board and package design.

[RobertG]

Apple to stick with Samsung for A8 chip, final manufacturing prep underway - report

By Shane Cole

Contrary to recent rumors, Samsung has won the contract to produce Apple's next-generation A-series processor and will do so at the same Texas facility that churns out the 64-bit A7 at the heart of the iPhone 5s and iPad Air, according to a new report from South Korea.

http://appleinsider.com/articles/14/03/10/apple-to-stick-with-samsung-for-a8-chip-final-manufacturing-prep-underway---report


Samsung's Austin, Texas semiconductor plant

An unnamed Samsung official told ZDNet Korea that a manufacturing agreement has already been signed and that engineers from both companies are working together to ramp up production. Shipments of the so-called "A8" will reportedly begin this fall, around the same time that many expect Apple to unveil new models of its mobile devices.

Apple's relationship with Samsung has been strained in recent years as the two companies are increasingly at each other's throat both in stores and in the courtroom. Samsung's position as the contract foundry for Apple's closely-guarded A-series processors, arguably the most important component in the company's top-selling iOS devices, is believed to be especially tenuous.

Taipei, Taiwan-based foundry TSMC — which already makes other, less high-profile chips for Apple — has been repeatedly tabbed as Samsung's successor for A-series chip production. As recently as last week, reports suggested that TSMC had taken over "most" of the orders for the A8, leaving Samsung as a secondary supplier.

This would not be the first time TSMC has been linked to Apple's flagship silicon, only to have Samsung retain the contract. Rumors pointed in TSMC's direction for both the A6X and A7 processors, and each of those chips eventually rolled off of Samsung's Austin, Texas production line.