Replies to post #24990 on Intel Corp (INTC)

[chipguy]

So the fact that the most die of the chipset "bin" at, say 800 MHz, but you sell them at 400 MHz (therefore all are sellable) vs. CPU that bins at 800 MHz (on the same process technology), but you need 4.5 GHz to be competitive plays no role?

That is where the difference in team size and design
methodology comes into play. Chipsets are like GPUs,
the life cycles are too short and profit margins too small
to support a four year high custom content design effort
like an MPU. So chipsets and GPUs are almost entirely
pure ASIC flow. The challenge in a chipset is to operate
at 400-500+ MHz and let address flow through from
FSB to memory and data between FSB and memory
with as absolutely few cycles of chip crossing latency
as possible even though there could be multiple clock
domains running asynchronously or at 2X the main
frequency.

You also seem very confused about binning. It costs
the same to make a low bin, mid bin, and high bin
MPU. The difference is what you can sell them for.


If you say that Intel can TODAY produce an 800 MHz Coppermine at the same cost as an average chipset sold today, you would be largely right. But Intel certainly could not do so at the same price 6 years ago. Intel employed army of men counted in 10s of thousands to squeeze the last MHz out of the Coppermine.

You confuse design effort with variable manufacturing
cost. There is very little correlation. In fact it can be
inverse. If I spend $50m NRE I might get a pure sea
of gates MPU that was 100 mm2. If I spend $250m
NRE I might get a high custom layout content MPU
that was 60 mm2. The latter will be cheaper to
manufacture.


Let me get this (since you didn't explicitly go out on the limb with wbmw). Do you agree with wbmw that Intel production cost of either a chipset or a CPU is roughly equal to $30? Something that, BTW, TSMC can do for SiS for some $15, and still make a profit?

Depends on the relative area, process, package, and
test particulars. A 100+ mm2 northbridge chip made
in 130 nm and packaged in a 1000+ I/O BGA might
cost Intel more to make than the 83 mm2, 130 nm
Banias P-M.

[Tenchu]

Joe, So the fact that the most die of the chipset "bin" at, say 800 MHz, but you sell them at 400 MHz (therefore all are sellable)

A chipset that can run at 400 MHz but bin out at 800 MHz? Wow, it's like the back-end design guys have the easiest job in the world.

I can tell that wasn't your point, but your point is becoming more and more obscure.

Tenchu