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chipguy

01/10/14 1:24 PM

#127071 RE: This Causes an Error #127036

The metal stack was optimized for performance rather than for density, yes, but the irony is that the low power 22nm chips didn't clock all that high at all!

As you raise supply voltage transistors get faster but wire delay
stays the same. Having fast interconnect means your wire delay
is not a bottleneck for large CPU cores clocking fast at medium
to high voltages (server and desktop).

Mobile chips have small CPUs running at low voltage so transistor
delay dominates and fast interconnect doesn't help.

That is why
1) Intel process advantage vs TSMC at similar node is minimal in
mobile.
2) Server chips made at TSMC are a joke vs Intel high end. So would
desktop class chips made at TSMC vs Intel but no one is stupid to
even try.