Replies to post #2951 on Advanced Micro Devices Inc (AMD)

[Elmer Phud]

Subzero -

"Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said

This doesn't speak to the 1 meg L2 or the memory controller or the aHT ports, but the .13u process should have bought back some of the gain, if not all.

[yourbankruptcy]

subzero, I have a feeling that this 104 mm^2 Sledgehammer they tried to produce for 2001 and this 2003 Opteron are completely different chips. I feel the real Sledgehammer is dead.

[j3pflynn]

subzero, 5% accounted for the 64-bit part only. It had nothing to do with the extra 768K of cache compared to the Athlon of the time!
Paul

[fyodor]

Paul: AMD PROMISED the Sledgehammer(now Opteron) would be only 5% greater than 104 sq. mm. on a 0.18 micron process.

No, that is not what AMD promised. As your own quoted piece states, "Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires".

The two statements are not the same.

If you actually sit down and do the calculations for the Opteron die, you'll find it fits pretty well. Download the high-rez die photo from AMD's site and load it into your favorite editor. Starting from a total die size of 193mm², subtract the memory controller, the memory interface, 75% of the L2 cache and 2 of the 3 HyperTransport interfaces. That brings us to around 79mm².

This is in .13µm of course (but is still *smaller* than any 130nm Athlon), but then you also need to take the lower density of the Opteron L2 cache over previous Athlons into account. Additionally, there is a "switch" of some kind that the 3 HyperTransport interfaces and the 128-bit wide memory controller connects to. Since it isn't marked on AMD's die photo, I don't know if I've removed it or not. There's also the assumption that no other changes have been made to the core, which certainly is not the case. There TLB has been doubled (IIRC!) and there are likely other changes as well. Lastly, there's also the (almost certainly false) assumption that a single HyperTransport interface (w. all the associated power and ground) takes up exactly as much as the EV6 interface on the old Athlon.

All in all, AMD's claim of a 5% increase in die size [of an Athlon Tbird] for adding 64-bit capability is quite credible. It's certainly well within the margins of error my assumptions above provide ;-).

-fyo