Re: Can you point to any reports of data corruption involving the 3.0 GHz P4?
The post was meant to be lighthearted, and was followed by a smiley. I thought it was a suitable reaction to all the boasting going on about how great the new chip was.
But lets look a little more closely. What problems are manifested as CPU problems?
The most common is the "doesn't boot every time" after a warm reset, or a cold boot (or both). This is bacause the most sensitive time for a CPU is when its multiple on board clocks are first starting up, and if one of the clocks "wakes up" out of order, the PC won't boot. You hit reset again, this time the on-board capacitors are still partly charged, and the machine boots fine. There have been systems like this, with problems like this, from both Intel and AMD (it's usually a motherboard problem, not a CPU problem, but a new CPU can often exacerbate the problem or cure it).
If a PC boots (and none of the testers reported any trouble) another thing it can do is hang, which will sometimes cause data corruption (and wasn't reported by any testers), or it just flat out silently makes a error 1 in a billion times or so, which will evenutally (maybe immediately) corrupt data.
Bottom line is that CPUs either have trouble booting, or they're perfect, or they corrupt data.
The new P4's boot fine, which leaves perfect or corrupts data. The new P4's were pulled, so they aren't perfect - that leaves corrupts data.
Judging by the lack of problems seen by testers, it's a 1 in billions event, but apparently it sometimes happens.
I love some of the careful wording like "It's only a speedpath error." The chips clocked fine, so a speedpath error means the chip was producing errors in its calculations, and that's how data gets corrupted. Or, "It's just an anomoly", as if an "anomoly" that makes the chip give the wrong answer is OK!
There were some Sparc chips that SUN shipped a few years ago in which a cache error was found after the chip was first benchmarked. SUN had to back off the cache timings (at first, they disabled one of the caches completely) and you should have heard the Intel guys whining about how SUN was cheating on their Spec scores etc. (SUN left posted their Spec scores from chips with the cache enabled at full speed until Intel demanded that they be taken down. Funny that Intel's PR bunnies aren't whinging bout the Spec scored from their own "anomolous" chips.