Replies to post #2034 on Advanced Micro Devices Inc (AMD)

[wbmw]

Chipguy, Re: Have you considered something as simple as this is the first
implementation of the K8 microarchitecture while AMD has re-implemented
the K7 microarchitecture around half a dozen times?

I was thinking the same thing. Of course, this points to a questionable design decision. Would it not have been better to simplify the changes between generations by limiting the number of new features? Perhaps AMD was too aggressive with their approach, and this led to more effort than they anticipated. A better approach might have been to go with Hypertransport, iMC, and x86-64, while leaving the core relatively unchanged.

[Elmer Phud]

Chipguy -

LOL, do you deny the fundamental physics that SOI eliminates the PN junction capacitance associated with the source and drain active areas of a MOSFET? Look at the capacitance breakdown on a typical net and do the math.

Please... Don't point me to a textbook, customers don't buy textbooks. Show me a product on both bulk silicon and SOI where SOI shows an advantage. The only one I know of is Hammer with their Athlon core and it shows a disadvantage.

Have you considered something as simple as this is the first
implementation of the K8 microarchitecture while AMD has re-implemented the K7 microarchitecture around half a dozen times? Maybe they've learned something along the way. Engineers tend to do that.

Hammer is a K7 with 2 more pipeline stages, a memory controller and aHT ports. The additional pipeline stages should have added to the frequency. Couple that with SOI and now we have a 15% reduction is speed, if expectations hold. I gave you an example of Intel adding a memory controller to their CPU core plus a graphics controller and seeing no speed degradation whatsoever compared to their mainstream cpu. All indications are that SOI does not deliver on it's promises, textbooks excepted.