Replies to post #1871 on Advanced Micro Devices Inc (AMD)

[UpNDown]

jhalada, on Opteron cache

I don't have any reference to the cache type, exclusive or inclusive. The complexity of keeping the cache exclusive seems to be counterproductive for Opterons though, especially when the caches are getting to the 512KB, 1MB and 2MB level.

So don't take this as a confirmation, but I don't see any way that the crossbar logic will be able to handle exclusive cache when keeping the caches coherent over cHT.

The Athlon-64 might be different, but that wouldn't make sense either. Too much differentiation makes for too much work.

[UpNDown]

jhalada, further (or less) on Opteron cache exclusivity

I looked through the x86-64 Architecture manuals for information on cache exclusivity. It seems to be left as implementation dependent and we are supposed to wait for the data sheets :).

The one mention I was able to turn up was in the System Programming Manual, Volume 2, page 193 where it says, in part:

The L2 cache can be exclusive, meaning it does not cache information contained in the L1 cache. Conversely, inclusive L2 caches contain a copy of the L1-cached information.