Replies to post #67462 on Advanced Micro Devices Inc (AMD)

[CombJelly]

"Could you put the impact of speeding up the P-channels a little more into layman's terms"

It means the logic cells can be smaller and probably faster. They should also be packed more efficiently on the die, which also helps with a smaller overall chip.

Here is a screenshot of an inverter using Cadence. Go all the way down, although you can go step by step.
http://www.ee.virginia.edu/~mrs8n/cadence/tutorial5.html.html
The green is the n-diffusion for the P-doped region. Below it is the N-doped region. The red is the polysilicon which makes up the gate. The blue is metal and the black squares are vias for contacts.

In most cases, they are paired, that is what puts the "Complementary" in CMOS. Here is a web page that shows how these things are wired up to make gates.

http://www.play-hookey.com/digital/electronics/cmos_gates.html