Replies to post #117609 on Intel Corp (INTC)

[Golfbum]

Looks like everyone but Intel in that forum and doesn't sound like the wannabees are very happy campers. Meanwhile Intel will be ramping 14nm soon.

gb

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How can anybody expect 14nm chips in 2014 from the non-Intel folks if nobody is even on 20nm yet?

Are we playing "skip the process node on paper"?

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How can anybody expect 14nm chips in 2014 from the non-Intel folks if nobody is even on 20nm yet?

Are we playing "skip the process node on paper"?

[wbmw]

Mas, your link holds a number of very key gems in it.

“We have these beautiful [3-D] transistors, but we can’t run them too far,” Jain said, noting “dynamic power [is] getting out of hand.” In addition, “those of us in high performance devices have not seen much improvement in core voltage scaling,” he said

I'd like to see the foundries' data on voltage scaling, and compare it to Intel's, since Intel has shown very aggressive voltage scaling, and excellent performance scaling at those low voltages. Their process and their design methodology seems to have been deeply tuned for this, which in my mind is the largest competitive advantage of their new process. Voltage scaling essentially allows Intel to build a more powerful design (like Haswell), and scale it down to low power to get the best of both worlds.

His group taped out a 20 nm test chip in April 2012 that showed working MIPI, PCI Express and USB interfaces using double patterning. A follow up 14 nm chip was a simpler device mainly focused on memory, and has not yet come back from the fab.

Read this in conjunction with this one:

In the race to catch up with Intel’s 22 nm FinFET process, now in production, foundries have agreed to take two separate steps, he said. First they are tackling at 20 nm the need for double patterning with 193-nm lithography. Then they are adding 14 nm FinFETs as “front end” devices in a node that still uses 20 nm “back end” interconnects, he said.

Did you catch that?

Essentially, they are admitting that the only test chip they have is (A) at 20nm and not 14nm, (B) uses double-patterning, when they are aiming to reduce the need for it. Let's focus on (B) first.

The idea of double-patterning is to get a wavelength of light at 193nm (which hasn't changed over the course of multiple process nodes) to etch features into 20nm silicon, and below. The only way to do that is to increase the number of patterning steps, each of which adds huge amounts of time and cost to the wafer development. The foundries succeeded in limiting the need for double-patterning at 28nm, but they'll likely need it at 20nm, let alone what they'll need to have reasonable yields at 14nm.

The downside is that as cost per wafer goes up, it defeats the cost savings from compacting the die on the new process. The SOC vendors still need to sell their SOC for $20 to win the sale, but now it costs more to manufacture. So one choice is to shrink the number of mm2 by reducing features and performance, but then - how do they win vs. Intel? It's a rock and a hard place.

Second is that their 14nm chip hasn't even come back yet, so they have no idea whether it will even function. And a device with memory cells on it is hardly going to be as useful in refining their tools as the chip they made with 20nm with several low power physical interfaces on it.

I think these guys will struggle.