Replies to post #65160 on Advanced Micro Devices Inc (AMD)

[chipguy]

Current interrupt driven OSes and heavy multitasking show that 8 way SA caches with the current methods of address bit swapping get overwhelmed.

I am feeling charitable today so I'll give you a free clue: look up
the meaning of the terms capacity miss and conflict miss. The
former is why an integrated FA cache will never significantly
outperform a reasonably set associative cache of the same
capacity (although a larger capacity SA cache is probably more
realistic for the same chip area when capacity is not restricted
to integer powers of two) on miss rate no matter how large a
degree of multitasking exists. The minor reduction in miss rate
for FA will *not* make up for its worse latency so the FA cache
will perform worse.

Here's another clue for you that should be obvious to everyone,
not just memory design experts. MPU architects could easily
put FA caches on chips if they wanted to but they don't. They
have access to enormous collections of performance and
trace data collected from real world applications and multi-
processing workloads and you don't.


They also take into account that the more ways have higher latencies, which a good FA design does not have

Absolute nonsense. You really don't have any clue how various
cache architectures are actually implemented in silicon.